SLVSHE3 June 2024 DRV2911-Q1
PRODUCTION DATA
The typical ULC application utilizes the host processor for configuring the ULC1001-Q1 controller, which subsequently drives a PWM signal to the DRV2911-Q1. The DRV2911-Q1 output may be passed through an LC filter before driving the piezo-based LCS. A sense resistor is placed in line with the OUTA driver output and has current sense connections on either side that route back to the controller device. Additionally, voltage sense connections across the LCS are routed to the controller.
When powering ULC1001-Q1 using the AVDD pin of DRV2911-Q1, the host processor must be used to control the DRV2911-Q1 RESETZ pin. Alternatively, RESETZ can be set high by using a resistive divider to PVDD. In the low-power reset mode (RESETZ = low), AVDD is disabled and powers down ULC1001-Q1.
When using an independent supply for ULC1001-Q1, the SDZ_OUT pin can be connected to RESETZ to control the DRV2911-Q1 functional mode using the ULC_TX_mode_cfg2 register. Additional DRV2911-Q1 hardware interface pin settings for SLEW and OCP are outlined in Hardware Interface and vary based on the system design.
Table 6-1 outlines recommendations for passive components shown in the schematic, Figure 7-2.
Lastly, the resistor values for R1 through R6 should be set based on the current and voltage levels required to drive the LCS. Refer to the next section Section 7.2.2 for details. R5 is pulled high to the VDD supply (1.8V) from ULC1001-Q1.