SLVSHE3 June   2024 DRV2911-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Stage
      2. 6.3.2 Hardware Interface
      3. 6.3.3 AVDD Linear Voltage Regulator
      4. 6.3.4 Step-Down Mixed-Mode Buck Regulator
        1. 6.3.4.1 Buck in Inductor Mode
        2. 6.3.4.2 Buck in Resistor mode
        3. 6.3.4.3 Buck Regulator with External LDO
        4. 6.3.4.4 AVDD Power Sequencing with Buck Regulator
        5. 6.3.4.5 Mixed mode Buck Operation and Control
        6. 6.3.4.6 Buck Undervoltage Lockout
        7. 6.3.4.7 Buck Overcurrent Protection
      5. 6.3.5 Charge Pump
      6. 6.3.6 Slew Rate Control
      7. 6.3.7 Cross Conduction (Dead Time)
      8. 6.3.8 Propagation Delay
      9. 6.3.9 Protections
        1. 6.3.9.1 PVDD Supply Undervoltage Lockout
        2. 6.3.9.2 AVDD Undervoltage Lockout
        3. 6.3.9.3 VCP Charge Pump Undervoltage Lockout
        4. 6.3.9.4 Overcurrent Latched Protection
        5. 6.3.9.5 Thermal Shutdown (OTSD)
          1. 6.3.9.5.1 OTSD FET
          2. 6.3.9.5.2 OTSD (Non-FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Reset Mode
        2. 6.4.1.2 Operating Mode
        3. 6.4.1.3 Fault Reset (RESETZ Pulse)
      2. 6.4.2 OUTOFF functionality
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Procedure
      2. 7.2.2 Voltage and Current Sense Circuitry
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Power Dissipation

The power loss in DRV2911-Q1 include standby power losses, LDO power losses, FET conduction and switching losses, and diode losses. The FET conduction loss dominates the total power dissipation in DRV2911-Q1. The total device dissipation is the power dissipated in each of the two half bridges added together. The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking. Note that RDS,ON increases with temperature, so as the device heats, the power dissipation increases. Take this into consideration when designing the PCB and heatsinking.

A summary of equations for calculating each loss is shown in Table 9-1.

Table 9-1 DRV2911-Q1 Power Loss Approximations

Loss type

Approximate Power Loss Calculation

Standby power

 Pstandby = VPVDD x IPVDD_TA

LDO

PLDO = (VPVDD-VAVDD) x IAVDD

FET conduction

 PCON = 2 x (IPK)2 x Rds,on(TA)

FET switching

 PSW = IPK x VPVDD x trise/fall x fPWM

Diode

 Pdiode = 2 x IPK x VF(diode)x tDEADTIME x fPWM