SLVSHE3 June   2024 DRV2911-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Stage
      2. 6.3.2 Hardware Interface
      3. 6.3.3 AVDD Linear Voltage Regulator
      4. 6.3.4 Step-Down Mixed-Mode Buck Regulator
        1. 6.3.4.1 Buck in Inductor Mode
        2. 6.3.4.2 Buck in Resistor mode
        3. 6.3.4.3 Buck Regulator with External LDO
        4. 6.3.4.4 AVDD Power Sequencing with Buck Regulator
        5. 6.3.4.5 Mixed mode Buck Operation and Control
        6. 6.3.4.6 Buck Undervoltage Lockout
        7. 6.3.4.7 Buck Overcurrent Protection
      5. 6.3.5 Charge Pump
      6. 6.3.6 Slew Rate Control
      7. 6.3.7 Cross Conduction (Dead Time)
      8. 6.3.8 Propagation Delay
      9. 6.3.9 Protections
        1. 6.3.9.1 PVDD Supply Undervoltage Lockout
        2. 6.3.9.2 AVDD Undervoltage Lockout
        3. 6.3.9.3 VCP Charge Pump Undervoltage Lockout
        4. 6.3.9.4 Overcurrent Latched Protection
        5. 6.3.9.5 Thermal Shutdown (OTSD)
          1. 6.3.9.5.1 OTSD FET
          2. 6.3.9.5.2 OTSD (Non-FET)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Reset Mode
        2. 6.4.1.2 Operating Mode
        3. 6.4.1.3 Fault Reset (RESETZ Pulse)
      2. 6.4.2 OUTOFF functionality
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Procedure
      2. 7.2.2 Voltage and Current Sense Circuitry
  9. 8 Power Supply Recommendations
    1. 8.1 Bulk Capacitance
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
      1. 9.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DRV2911-Q1 DRV2911-Q140-Pin VQFN With Thermal Pad DownTop ViewFigure 4-1 DRV2911-Q140-Pin VQFN With Thermal Pad DownTop View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
NC 1, 19, 20, 38, 39, 40

NC

 No connection, open.
AGND 2, 26, 31, 36 GND Device analog ground. Refer to Section 9.1 for connecting recommendations.
FB_BK 3 PWR I Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor.
GND_BK 4 GND Buck regulator ground. Refer to Section 9.1 for connection recommendations.
SW_BK 5 PWR O Buck switch node. Connect this pin to an inductor or resistor.
CPL 6 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
CPH 7 PWR
CP 8 PWR O Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and PVDD pins.
PVDD 9, 10, 11 PWR I Power supply. Connect to supply voltage; bypass to PGND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for PVDD. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
PGND 12, 15, 18 GND Device power ground. Refer to Section 9.1 for connections recommendation.
OUTA 13, 14 PWR O Half bridge output A.
OUTB 16, 17 PWR O Half bridge output B.
OUTOFF 21 I When this pin is logic high the four MOSFETs in the power stage are turned OFF making all outputs Hi-Z.
FAULTZ 22 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to AVDD or an external source. Ensure that FAULTZ is pulled > 2.2V on power up.
RESETZ 23 I Driver RESETZ. When this pin is logic low, the device goes into a low-power sleep mode. A 20 to 40-µs low pulse can be used to reset fault conditions without entering sleep mode.
VSEL_BK 24 I Buck output voltage setting. This pin is a 2-level input pin set by an external resistor. Refer to Figure 6-2.
AVDD 25, 28, 30,

32

 PWR O 3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the AVDD (near pin 25) and AGND pins. This regulator can source up to 30 mA externally.
PWMA 27 I PWM input for half-bridge A control.
PWMB 29 I PWM input for half-bridge B control.
RBIAS 33 I Tie 47 kΩ resistor to AVDD.
SLEW 34 I Slew rate control setting. This pin is a 4-level input pin set by an external resistor. Refer to Figure 6-2.
OCP 35 I OCP level control setting. Refer to Figure 6-2.
VREF 37 PWR Connect a X5R or X7R, 0.1-μF, 6.3-V ceramic capacitor between the VREF and AGND pins.
Thermal pad GND Must be connected to analog ground.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect