SLVSCV1E September   2015  – February 2017 DRV3205-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Serial Peripheral Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Programming
      1. 7.3.1 SPI
        1. 7.3.1.1 Address Mode Transfer
          1. 7.3.1.1.1 SPI Address Transfer Phase
        2. 7.3.1.2 SPI Data Transfer Phase
        3. 7.3.1.3 Device Data Response
    4. 7.4 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Three-Phase Motor Drive-Device for Automotive Application
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PHP PowerPAD™ Package
48-Pin HTQFP
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 GLS3 PWR Gate low-side 3, connected to gate of external power MOSFET.
2 SLS3 PWR Source low-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
3 GHS3 PWR Gate high-side 3, connected to gate of external power MOSFET.
4 SHS3 PWR Source high-side 3, connected to external power MOSFET for gate discharge and VDS monitoring.
5 VSH HVI_A Sense high-side, sensing VS connection of the external power MOSFETs for VDS monitoring.
6 SHS2 PWR Source high-side 2, connected to external power MOSFET gate discharge and VDS monitoring.
7 GHS2 PWR Gate high-side 2, connected to gate of external power MOSFET.
8 SLS2 PWR Source low-side 2, connected to external power MOSFET for gate discharge and VDS monitoring.
9 GLS2 PWR Gate low-side 2, connected to gate of external power MOSFET.
10 TEST HVI_A Test mode input, during normal application connected to ground.
11 GLS1 PWR Gate low-side 1, connected to gate of external power MOSFET.
12 SLS1 PWR Source low-side 1, connected to external power MOSFET for gate discharge and VDS monitoring.
13 GHS1 PWR Gate high-side 1, connected to gate of external power MOS transistor.
14 SHS1 PWR Source high-side 1, connected to external power MOS transistor for gate discharge and VDS.
15 VS Supply Power-supply voltage (externally protected against reverse battery connection).
16 GNDA GND Analog ground.
17 ERR LVO_D Error (low active), Error pin to indicate detected error.
18 DRVOFF HVI_D Driver OFF (high active), secondary bridge driver disable.
19 RVSET HVI_A VDDIO / ADREF OV/UV configuration resister.
20 BOOST Supply Boost output voltage, used as supply for the gate drivers.
21 SW PWR Boost converter switching node connected to external coil and external diode.
22 NCS HVI_D SPI chip select.
23 GNDLS_B GND Boost GND to set current limit. Boost switching current goes through this pin through external resistor to ground.
24 EN HVI_D Enable (high active) of the device.
25 VDDIO Supply I/O supply voltage, defines the interface voltage of digital I/O, for example, SPI.
26 SCLK HVI_D SPI clock.
27 SDO LVO_D SPI data output.
28 SDI HVI_D SPI data input.
29 VCC3 LVO_A VCC3 regulator, for internal use only. TI recommends an external decoupling capacitor of 0.1 µF. External load < 100 µA.
30 GNDA GND Analog ground.
31 RO LVO_A Analog output.
32 VCC5 LVO_A VCC5 regulator, for internal use only. Recommended external decoupling capacitor 1 µF. External load < 100 µA.
33 ADREF LVI_A ADC reference of MCU, used as maximum voltage clamp for O1 to O3.
34 O1 LVO_A Output current sense amplifier 1.
35 O2 LVO_A Output current sense amplifier 2.
36 O3 LVO_A Output current sense amplifier 3.
37 IN3 LVI_A Current sense negative input 3.
38 IP3 LVI_A Current sense positive input 3.
39 IN2 LVI_A Current sense input N 2.
40 IP2 LVI_A Current sense input P 2.
41 IN1 LVI_A Current sense input N 1.
42 IP1 LVI_A Current sense input P 1.
43 IHS3 HVI_D High-side input 3, digital input to drive the HS3.
44 IHS2 HVI_D Input HS 2, digital input to drive the HS2.
45 IHS1 HVI_D Input HS 1, digital input to drive the HS1.
46 ILS3 HVI_D Low-side input 3, digital input to drive the LS3.
47 ILS2 HVI_D Input LS 2, digital input to drive the LS2.
48 ILS1 HVI_D Input LS 1, digital input to drive the LS1.
(1) Description of pin type: GND = Ground; HVI_A = High-voltage input analog; HVI_D = High-voltage input digital; LVI_A = Low-voltage input analog; LVO_A = Low-voltage output analog; LVO_D = Low-voltage output digital; NC = No connect; PWR = Power output; Supply = Supply input