SLVSHN6A December   2023  – June 2024 DRV3946-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Mechanical, Packaging, and Orderable Information
    1. 5.1 Package Option Addendum
    2. 5.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The DRV3946-Q1 is a highly integrated solution to drive two solenoids for automotive applications such as contactor relays in EV battery management systems. It includes power supplies, current sensing and current regulation, configurable peak and hold currents and associated timings, and diagnostics and protection functions. It also incorporates several unique functions that enhance performance compared to traditional discrete solenoid drivers. These functions include integrated redundant clamp circuits to quickly discharge the load current, an addressable SPI, and modified half-bridge driver stage with low on-resistance switches.

The device controls solenoid loads through a single wire low-side connection and can pair with an external high-side switch (that can be shared) for redundant shut-off function. Integrated switches perform charging, recirculation and clamping. The device supports internal and external current control modes. The PWM frequency is configurable, with added low frequency dithering using automatic pseudo random frequencies generation and wave shaping. Internal PWM current control loop leads to reduced software development, since MCU current control loop is not needed. The DRV3946-Q1 supports flexible current control parameters to support wide range of solenoid types. Configurable peak and hold current and corresponding timing parameters allow system level power saving.

The DRV3946-Q1 is targeted to be functional safety-compliant, with ASIL-C rated functional safety goal for relay control and avoiding unintended operation. The device supports comprehensive protection and diagnostic features, such as continuous monitoring of load for open and short detection, on and off-state diagnostics, voltage monitors, short protection and high voltage rated IOs.

An addressable SPI allows multiple devices to be controlled on a shared SPI bus. In addition to reducing required MCU resources, the addressable SPI incorporates a broadcast command structure that can enable all devices on the shared addressed bus to take certain actions simultaneously. The SPI incorporates multiple robustness functions including a CRC, address readback capability, and various bus fault detection mechanisms.

DRV3946-Q1 Simplified Schematic Simplified Schematic