SLIS164E December   2014  – September 2016 DRV5033-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Magnetic Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Field Direction Definition
      2. 7.3.2 Device Output
      3. 7.3.3 Power-On Time
      4. 7.3.4 Output Stage
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Load Dump Protection
        3. 7.3.5.3 Reverse Supply Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Standard Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Configuration Example
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Two-Wire Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DRV5033-Q1 device is a chopper-stabilized hall sensor with a digital omnipolar switch output for magnetic sensing applications. The DRV5033-Q1 device can be powered with a supply voltage between 2.7 and 38 V, and will survive –22 V reverse battery conditions continuously. Note that the DRV5033-Q1 device will not be operating when about –22 to 2.4 V is applied to VCC (with respect to GND). In addition, the device can withstand voltages up to 40 V for transient durations.

The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field.

The omnipolar configuration allows the hall sensor to respond to either a south or north pole. A strong magnetic field of either polarity will cause the output to pull low (operate point, BOP), and a weaker magnetic field will cause the output to release (release point, BRP). Hysteresis is included in between the operate and release points, so magnetic field noise will not trip the output accidentally.

An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to VCC, or to a different voltage supply. This allows for easier interfacing with controller circuits.

7.2 Functional Block Diagram

DRV5033-Q1 fbd_slis162.gif

7.3 Feature Description

7.3.1 Field Direction Definition

A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 11.

DRV5033-Q1 field_direction_slis150.gif
N = North pole, S = South pole
Figure 11. Field Direction Definition

7.3.2 Device Output

If the device is powered on with a magnetic field strength between BRP and BOP, then the device output is indeterminate and can either be Hi-Z or Low. If the field strength is greater than BOP, then the output is pulled low. If the field strength is less than BRP, then the output is released.

DRV5033-Q1 figure_12_lis152.gif Figure 12. DRV5033-Q1—BOP > 0

7.3.3 Power-On Time

After applying VCC to the DRV5033-Q1 device, ton must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 13 and Figure 14 occurs at the end of ton. This pulse can allow the host processor to determine when the DRV5033-Q1 output is valid after startup. In Case 1 (Figure 13) and Case 2 (Figure 14), the output is defined assuming a constant magnetic field B > BOP and B < BRP.

DRV5033-Q1 timing_case1_slis150.gif Figure 13. Case 1: Power On When B > BOP
DRV5033-Q1 timing_case2_slis150.gif Figure 14. Case 2: Power On When B < BRP

If the device is powered on with the magnetic field strength BRP < B < BOP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until ton has elapsed. At the end of ton, a pulse is given on the OUT pin to indicate that ton has elapsed. After ton, if the magnetic field changes such that BOP < B, the output is released. Case 3 (Figure 15) and Case 4 (Figure 16) show examples of this behavior.

DRV5033-Q1 timing_case3_slis150.gif Figure 15. Case 3: Power On When BRP < B < BOP, Followed by B > BOP
DRV5033-Q1 timing_case4_slis150.gif Figure 16. Case 4: Power On When BRP < B < BOP, Followed by B < BRP

7.3.4 Output Stage

The DRV5033-Q1 output stage uses an open-drain NMOS, and it is rated to sink up to 30 mA of current. For proper operation, calculate the value of the pullup resistor R1 using Equation 1.

Equation 1. DRV5033-Q1 eq_01_slis150.gif

The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching.

In addition, ensure that the value of R1 > 500 Ω to ensure the output driver can pull the OUT pin close to GND.

NOTE

Vref is not restricted to VCC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings.
DRV5033-Q1 circuit_vref_slis150.gif Figure 17.

Select a value for C2 based on the system bandwidth specifications as shown in Equation 2.

Equation 2. DRV5033-Q1 eq_02_slis150.gif

Most applications do no require this C2 filtering capacitor.

7.3.5 Protection Circuits

The DRV5033-Q1 device is fully protected against overcurrent and reverse-supply conditions.

7.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.

7.3.5.2 Load Dump Protection

The DRV5033-Q1 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand VCC = 40 V. No current-limiting series resistor is required for this protection.

7.3.5.3 Reverse Supply Protection

The DRV5033-Q1 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).

NOTE

In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.

Table 1.

FAULT CONDITION DEVICE DESCRIPTION RECOVERY
FET overload (OCP) ISINK ≥ IOCP Operating Output current is clamped to IOCP IO < IOCP
Load dump 38 V < VCC < 40 V Operating Device will operate for a transient duration VCC ≤ 38 V
Reverse supply –22 V < VCC < 0 V Disabled Device will survive this condition VCC ≥ 2.7 V

7.4 Device Functional Modes

The DRV5033-Q1 device is active only when VCC is between 2.7 and 38 V.

When a reverse supply condition exists, the device is inactive.