SLIS154A December 2014 – December 2015 DRV5053-Q1
PRODUCTION DATA.
The DRV5053-Q1 device is a chopper-stabilized Hall sensor with an analog output for magnetic sensing applications. The DRV5053-Q1 device can be powered with a supply voltage between 2.7 and 38 V, and will survive –22 V reverse battery conditions continuously. Note that the DRV5053-Q1 device will not be operating when approximately –22 to 2.4 V is applied to VCC (with respect to GND). In addition, the device can withstand supply voltages up to 40 V for transient durations.
The output voltage is dependent on the magnetic field perpendicular to the package. The absence of a magnetic field will result in OUT = 1 V. A magnetic field will cause the output voltage to change linearly with the magnetic field.
The field polarity is defined as follows: a south pole near the marked side of the package is a positive magnetic field. A north pole near the marked side of the package is a negative magnetic field.
For devices with a negative sensitivity (that is, DRV5053RA: –40 mV/mT), a south pole will cause the output voltage to drop below 1 V, and a north pole will cause the output to rise above 1 V.
For devices with a positive sensitivity (that is, DRV5053EA: +40 mV/mT), a south pole will cause the output voltage to rise above 1 V, and a north pole will cause the output to drop below 1 V.
A positive magnetic field is defined as a south pole near the marked side of the package as shown in Figure 7.
The DRV5053-Q1 device output is defined below for negative sensitivity (that is, –45 mV/mT, RA) and positive sensitivity (that is, +45 mV/mT, EA):
After applying VCC to the DRV5053-Q1 device, ton must elapse before OUT is valid. Figure 10 shows Case 1 and Figure 11 shows case 2; the output is defined assuming a negative sensitivity device and a constant magnetic field –BSAT < B < BSAT.
The DRV5053-Q1 output stage is capable of up to 300-μA of current source or 2.3-mA sink. For proper operation, ensure that equivalent output load ROUT > 10 kΩ.
The capacitive load directly present on the OUT pin should be less than 10 nF to ensure the internal operational amplifier is stable. If an external RC filter is added to reduce noise, it is acceptable to use a resistor ≥ 200 Ω with a capacitor ≤0.1 µF. For an application example, see Filtered Typical Application.
An analog current limit circuit limits the current through the output driver. The driver current will be clamped to IOCP
An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.
The DRV5053-Q1 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand VCC = 40 V. No current-limiting series resistor is required for this protection.
The DRV5053-Q1 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).
NOTE
In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.
FAULT | CONDITION | DEVICE | DESCRIPTION | RECOVERY |
---|---|---|---|---|
FET overload (OCP) | ISINK ≥ IOCP | Operating | Output current is clamped to IOCP | IO < IOCP |
Load Dump | 38 V < VCC < 40 V | Operating | Device will operate for a transient duration | VCC ≤ 38 V |
Reverse Supply | –22 V < VCC < 0 V | Disabled | Device will survive this condition | VCC ≥ 2.7 V |
The DRV5053-Q1 device is active only when VCC is between 2.7 and 38 V.
When a reverse supply condition exists, the device is inactive.