SBAS644B April   2018  – June 2020 DRV5056

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Schematic
      2.      Magnetic Response
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Magnetic Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Magnetic Flux Direction
      2. 7.3.2 Magnetic Response
      3. 7.3.3 Sensitivity Linearity
      4. 7.3.4 Ratiometric Architecture
      5. 7.3.5 Operating VCC Ranges
      6. 7.3.6 Sensitivity Temperature Compensation For Magnets
      7. 7.3.7 Power-On Time
      8. 7.3.8 Hall Element Location
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Selecting the Sensitivity Option
      2. 8.1.2 Temperature Compensation for Magnets
      3. 8.1.3 Adding a Low-Pass Filter
      4. 8.1.4 Designing for Wire Break Detection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Magnetic Characteristics

for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VQ Quiescent voltage B = 0 mT, TA = 25°C DRV5056A1/Z1 0.535 0.6 0.665 V
DRV5056A2/Z2, DRV5056A6 0.54 0.6 0.66
DRV5056A3/Z3, DRV5056A4/Z4 0.55 0.6 0.65
VQΔT Quiescent voltage temperature drift B = 0 mT,
TA = –40°C to 125°C versus 25°C		 VCC = 5 V 0.08 V
VCC = 3.3 V 0.04
VQΔL Quiescent voltage lifetime drift High-temperature operating stress for 1000 hours < 0.5%
S Sensitivity VCC = 5 V,
TA = 25°C		 DRV5056A1/Z1 190 200 210 mV/mT
DRV5056A2/Z2, DRV5056A6 95 100 105
DRV5056A3/Z3 47.5 50 52.5
DRV5056A4/Z4 23.8 25 26.2
VCC = 3.3 V,
TA = 25°C		 DRV5056A1/Z1 114 120 126
DRV5056A2/Z2, DRV5056A6 57 60 63
DRV5056A3/Z3 28.5 30 31.5
DRV5056A4/Z4 14.3 15 15.8
BL Linear magnetic sensing range(2) VCC = 5 V,
TA = 25°C		 DRV5056A1/Z1 20 mT
DRV5056A2/Z2, DRV5056A6 39
DRV5056A3/Z3 79
DRV5056A4/Z4 158
VCC = 3.3 V,
TA = 25°C		 DRV5056A1/Z1 19
DRV5056A2/Z2, DRV5056A6 39
DRV5056A3/Z3 78
DRV5056A4/Z4 155
VL Linear range of output voltage(3) VQ VCC – 0.2 V
STC Sensitivity temperature compensation for magnets(4) DRV5056A6 0.05 0.12 0.19 %/°C
STC Sensitivity temperature compensation for magnets(4) DRV5056A1, DRV5056A2, DRV5056A3, DRV5056A4 0.12 %/°C
STCz Sensitivity temperature compensation for magnets(4) DRV5056Z1, DRV5056Z2, DRV5056Z3, DRV5056Z4 0 %/°C
SLE Sensitivity linearity error(3) VOUT is within VL ±1%
SRE Sensitivity ratiometry error(5) TA = 25°C,
with respect to VCC = 3.3 V or 5 V 		-2.5% 2.5%
SΔL Sensitivity lifetime drift High-temperature operating stress for 1000 hours < 0.5%
(1) B is the applied magnetic flux density.
(2) BL describes the minimum linear sensing range at 25°C taking into account the maximum VQ and Sensitivity tolerances.
(3) See the Sensitivity Linearity section.
(4) STC describes the rate the device increases Sensitivity with temperature. For more information, see the Sensitivity Temperature Compensation For Magnets section.
(5) See the Ratiometric Architecture section.