SBAS646A November 2018 – August 2020 DRV5057
PRODUCTION DATA
The accuracy and resolution for the methods described in the Section 8.1.2.1.1 and Section 8.1.2.1.2 sections depends significantly on the timer sampling frequency. Equation 2 calculates the least significant bit of the duty cycle (%DLSB) based on the chosen timer sampling frequency.
For example, with a 2-kHz PWM and a 400-kHz sampling frequency, the %DLSB is:
(2 kHz / 400 kHz) × 100 = 0.5%DLSB
If the sampling frequency in increased to 2-MHz, the %DLSB is improved to be:
(2 MHz / 400 kHz) × 100 = 0.1%DLSB
However, accuracy and resolution are still subject to noise and sensitivity.