SLVSGJ9 May   2024 DRV7308

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Absolute Maximum Ratings
  7. 6 ESD Ratings
  8. 7 Recommended Operating Conditions
  9. 8 Thermal Information
  10. 9 Electrical Characteristics
  11. 10Timing Diagrams
  12. 11Typical Characteristics
  13. 12Detailed Description
    1. 12.1 Overview
    2. 12.2 Functional Block Diagram
    3. 12.3 Feature Description
      1. 12.3.1 Output Stage
      2. 12.3.2 Input Control Logic
      3. 12.3.3 ENABLE (EN) Pin Function
      4. 12.3.4 Temperature Sensor Output (VTEMP)
      5. 12.3.5 Brake Function
      6. 12.3.6 Slew Rate Control (SR)
      7. 12.3.7 Dead Time
      8. 12.3.8 Current Limit Functionaity (ILIMIT)
      9. 12.3.9 Pin Diagrams
        1. 12.3.9.1 Four-Level Input Pin
        2. 12.3.9.2 Open-Drain Pin
        3. 12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
    4. 12.4 Protections
      1. 12.4.1 GVDD Undervoltage Lockout
      2. 12.4.2 Bootstrap Undervoltage Lockout
      3. 12.4.3 Current Limit Protection
      4. 12.4.4 GaNFET Overcurrent Protection
      5. 12.4.5 Thermal Shutdown (OTS)
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • REN|68
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.3.2 Input Control Logic

The DRV7308 controls the state of the GaN FET based on the PWM input signals at the INHx and INLx pins. The device uses the BRAKE signal to apply brake to motor drive. A logic high at the BRAKE signal overrides the INHx and INLx pins and turns on all low side GaN transistors. The device enters shutoff mode (all the gate drivers and GaN FETs in off state) and ignores the status of the INHx, INLx, and BRAKE pins when a logic low on the EN pin occurs. A 20-40μs logic low pulse at the EN pin resets the device from OCP and OTP faults. The truth table for the input control logic is shown in Table 12-2.

Table 12-2 Input Control Logic
EN BRAKE INHx INLx HIGH SIDE GAN FET LOW SIDE GAN FET DESCRIPTION
0 X X X OFF OFF Device in shutdown and all outputs in Hi-Z
1 1 X X OFF ON BRAKE. All low side GaN FETs are ON and all high-side GaN FETs are OFF
1 0 1 1 OFF OFF OUTx in Hi-Z
1 0 0 0 OFF OFF OUTx in Hi-Z
1 0 1 0 ON OFF OUTx connected to VM
1 0 0 1 OFF ON OUTx connected to SLx node