SLVSGJ9 May   2024 DRV7308

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Absolute Maximum Ratings
  7. 6 ESD Ratings
  8. 7 Recommended Operating Conditions
  9. 8 Thermal Information
  10. 9 Electrical Characteristics
  11. 10Timing Diagrams
  12. 11Typical Characteristics
  13. 12Detailed Description
    1. 12.1 Overview
    2. 12.2 Functional Block Diagram
    3. 12.3 Feature Description
      1. 12.3.1 Output Stage
      2. 12.3.2 Input Control Logic
      3. 12.3.3 ENABLE (EN) Pin Function
      4. 12.3.4 Temperature Sensor Output (VTEMP)
      5. 12.3.5 Brake Function
      6. 12.3.6 Slew Rate Control (SR)
      7. 12.3.7 Dead Time
      8. 12.3.8 Current Limit Functionaity (ILIMIT)
      9. 12.3.9 Pin Diagrams
        1. 12.3.9.1 Four-Level Input Pin
        2. 12.3.9.2 Open-Drain Pin
        3. 12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
    4. 12.4 Protections
      1. 12.4.1 GVDD Undervoltage Lockout
      2. 12.4.2 Bootstrap Undervoltage Lockout
      3. 12.4.3 Current Limit Protection
      4. 12.4.4 GaNFET Overcurrent Protection
      5. 12.4.5 Thermal Shutdown (OTS)
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • REN|68
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DRV7308 DRV7308 VQFN With Exposed Thermal Pad Top View Figure 4-1 DRV7308 VQFN With Exposed Thermal Pad Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AMPIN- 5 I Inverting input of the operational amplifier
AMPIN+ 6 I Non-inverting input of the operational amplifier
AMPOUT 4 O Output terminal of the operational amplifier
BOOTA 48 P Bootstrap supply for phase A; bypass to OUTA with a GVDD rated capacitor
BOOTB 43 P Bootstrap supply for phase B; bypass to OUTB with a GVDD rated capacitor
BOOTC 41 P Bootstrap supply for phase C; bypass to OUTC with a GVDD rated capacitor
BRAKE 25 I Motor Brake signal. Logic high on the pin turns on all the low side GaNFETs and turns off all the high side GaNFETs
EN 64 I Driver enable pin. When this pin is logic low the device goes to shutdown mode and all the GaN FETs are turned off. A 20µs to 40µs low pulse can be used to reset fault conditions
HV_nFAULT 26 O Fault indication pin. Pulled logic-low on fault condition; open-drain output requires an external pullup
ILIMIT 2 I Reference voltage for over current limit for internal comparator
INHA 18 I High-side driver control input for OUTA. This pin controls the output of the high-side GaNFET
INHB 20 I High-side driver control input for OUTB. This pin controls the output of the high-side GaNFET
INHC 22 I High-side driver control input for OUTC. This pin controls the output of the high-side GaNFET
INLA 19 I Low-side driver control input for OUTA. This pin controls the output of the Low-side GaNFET
INLB 21 I Low-side driver control input for OUTB. This pin controls the output of the Low-side GaNFET
INLC 24 I Low-side driver control input for OUTC. This pin controls the output of the Low-side GaNFET
NC 1, 23 No connect, can be connected to PGND
NC_A 49 I Can be connected to OUTA
NC_B 44 I Can be connected to OUTB
NC_C 40 I Can be connected to OUTC
OUTA 50-57 P Half bridge output A
OUTB 42, 45-47, 72 P Half bridge output B
OUTC 32-39 P Half bridge output C
PGND 7, 17, 27,28,29, 60,61,62,66, 70, 71 G Device power and signal ground. Connect to system ground
SLA 8, 9, 10, 67 P Phase A half bridge low side source
SLB 11, 12, 13, 68 P Phase B half bridge low side source
SLC 14, 15, 16, 69 P Phase C half bridge low side source
SR 65 I OUTx voltage slew rate control. Connect a resistor between SR pin and PGND or SR pin to GVDD to configure the slew rate
GVDD 63 P Low voltage power supply; bypass to PGND with one 1µF, GVDD rated ceramic capacitor plus one bulk capacitor rated for GVDD
VM 30, 31, 58, 59 P Power supply. Connect to motor supply voltage; bypass to PGND with a 0.1µF capacitor plus one bulk capacitor rated for VM
VTEMP 3 O Temperature Sensor Output
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.