SLVSGJ9 May   2024 DRV7308

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Absolute Maximum Ratings
  7. 6 ESD Ratings
  8. 7 Recommended Operating Conditions
  9. 8 Thermal Information
  10. 9 Electrical Characteristics
  11. 10Timing Diagrams
  12. 11Typical Characteristics
  13. 12Detailed Description
    1. 12.1 Overview
    2. 12.2 Functional Block Diagram
    3. 12.3 Feature Description
      1. 12.3.1 Output Stage
      2. 12.3.2 Input Control Logic
      3. 12.3.3 ENABLE (EN) Pin Function
      4. 12.3.4 Temperature Sensor Output (VTEMP)
      5. 12.3.5 Brake Function
      6. 12.3.6 Slew Rate Control (SR)
      7. 12.3.7 Dead Time
      8. 12.3.8 Current Limit Functionaity (ILIMIT)
      9. 12.3.9 Pin Diagrams
        1. 12.3.9.1 Four-Level Input Pin
        2. 12.3.9.2 Open-Drain Pin
        3. 12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
    4. 12.4 Protections
      1. 12.4.1 GVDD Undervoltage Lockout
      2. 12.4.2 Bootstrap Undervoltage Lockout
      3. 12.4.3 Current Limit Protection
      4. 12.4.4 GaNFET Overcurrent Protection
      5. 12.4.5 Thermal Shutdown (OTS)
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • REN|68
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.4 Protections

The DRV7308 integrates GaN FET overcurrent protection (GaN_OCP), overtemperature shutdown (OTSD), GVDD and bootstrap supply undervoltage protection (GVDD_UVLO and VBOOT_UVLO), and current limit (ILIMIT). Table 12-3 summarizes various faults details.

Table 12-3 Fault Action and Response
FAULT CONDITION REPORT GAN BRIDGE RECOVERY
GaN overcurrent protection (GaN_OCP) GaN FET current > IOCP HV_nFAULT All GaN pre-drivers turn off resulting Hi-Z (all three phases) Latched. 20μs to 40μs toggling pulse on EN pin or GVDD power recycling
SLx overcurrent limit (OCL) V SLx> VILIMIT HV_nFAULT All GaN pre-drivers turn off resulting Hi-Z (all three phases) Retry. After a fault clear time > tF_CLR
GVDD undervoltage VGVDD < VGVDD_UV HV_nFAULT All GaN pre-drivers turn off resulting Hi-Z (all three phases) Automatic: VGVDD_UVLO > VGVDD_UVLO_ON
Boot supply undervoltage (voltage between BOOTx and OUTx pin) VBOOTx < VBST_UV - The impacted high-side GaN pre-drivers turn off. All other GaNFETs continue to operate. Automatic: VBOOTx > VBST_UV_ON
Thermal shutdown (OTSD) TJ > TSD, for any GaNFET HV_nFAULT All GaN pre-drivers turns off resulting Hi-Z (all three phases) Latched. 20μs to 40μs toggling pulse on EN pin or GVDD power recycling