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DRV8000-Q1 Automotive Highly-integrated, Multi-function Driver for Door Control
SLVSH22
May 2024
DRV8000-Q1
ADVANCE INFORMATION
CONTENTS
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DRV8000-Q1 Automotive Highly-integrated, Multi-function Driver for Door Control
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings Auto
6.3
Recommended Operating Conditions
6.4
Thermal Information RGZ package
6.5
Electrical Characteristics
6.6
Timing Requirements
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
External Components
7.4
Feature Description
7.4.1
Heater MOSFET Driver
7.4.1.1
Heater MOSFET Driver Control
7.4.1.2
Heater MOSFET Driver Protection
7.4.1.2.1
Heater SH_HS Internal Diode
7.4.1.2.2
Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
7.4.1.2.3
Heater MOSFET Open Load Detection
7.4.2
High-side Drivers
7.4.2.1
High-side Driver Control
7.4.2.1.1
High-side Driver PWM Generator
7.4.2.1.2
Constant Current Mode
7.4.2.1.3
OUT7 HS ITRIP Behavior
7.4.2.1.4
High-side Drivers - Parallel Outputs
7.4.2.2
High-side Driver Protection Circuits
7.4.2.2.1
High-side Drivers Internal Diode
7.4.2.2.2
High-side Driver Over Current Protection
7.4.2.2.3
High-side Driver Open Load Detection
7.4.3
Electro-chromic Glass Driver
7.4.3.1
Electro-chromic Driver Control
7.4.3.2
Electro-chromic Driver Protection
7.4.4
Half-bridge Drivers
7.4.4.1
Half-bridge Control
7.4.4.2
Half-bridge ITRIP Regulation
7.4.4.3
Half-bridge Protection and Diagnostics
7.4.4.3.1
Half-bridge Off-State Diagnostics (OLP)
7.4.4.3.2
Half-Bridge Active Open Load Detection (OLA)
7.4.4.3.3
Half-Bridge Over-Current Protection
7.4.5
Gate Drivers
7.4.5.1
Input PWM Modes
7.4.5.1.1
Half-Bridge Control
7.4.5.1.2
H-Bridge Control
7.4.5.1.3
DRVOFF - Gate Driver Shutoff Pin
7.4.5.2
Smart Gate Driver - Functional Block Diagram
7.4.5.2.1
Smart Gate Driver
7.4.5.2.2
Functional Block Diagram
7.4.5.2.3
Slew Rate Control (IDRIVE)
7.4.5.2.4
Gate Driver State Machine (TDRIVE)
7.4.5.2.4.1
tDRIVE Calculation Example
7.4.5.2.5
Propagation Delay Reduction (PDR)
7.4.5.2.6
PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
7.4.5.2.6.1
PDR Pre-Charge/Pre-Discharge Setup
7.4.5.2.7
PDR Post-Charge/Post-Discharge Control Loop Operation Details
7.4.5.2.7.1
PDR Post-Charge/Post-Discharge Setup
7.4.5.2.8
Detecting Drive and Freewheel MOSFET
7.4.5.2.9
Automatic Duty Cycle Compensation (DCC)
7.4.5.2.10
Closed Loop Slew Time Control (STC)
7.4.5.2.10.1
STC Control Loop Setup
7.4.5.3
Tripler (Double-Stage) Charge Pump
7.4.5.4
Wide Common Mode Differential Current Shunt Amplifier
7.4.5.5
Gate Driver Protection Circuits
7.4.5.5.1
MOSFET VDS Overcurrent Protection (VDS_OCP)
7.4.5.5.2
Gate Driver Fault (VGS_GDF)
7.4.5.5.3
Offline Short Circuit and Open Load Detection (OOL and OSC)
7.4.6
Sense Output (IPROPI)
7.4.7
Protection Circuits
7.4.7.1
Fault Reset (CLR_FLT)
7.4.7.2
DVDD Logic Supply Power on Reset (DVDD_POR)
7.4.7.3
PVDD Supply Undervoltage Monitor (PVDD_UV)
7.4.7.4
PVDD Supply Overvoltage Monitor (PVDD_OV)
7.4.7.5
VCP Charge Pump Undervoltage Lockout (VCP_UV)
7.4.7.6
Thermal Clusters
7.4.7.7
Watchdog Timer
7.4.7.8
Fault Detection and Response Summary Table
7.5
Programming
7.5.1
SPI Interface
7.5.2
SPI Format
7.5.3
Timing Diagrams
8
DRV8000-Q1 Register Map
9
DRV8000-Q1_STATUS Registers
10
DRV8000-Q1_CNFG Registers
11
DRV8000-Q1_CTRL Registers
12
Application and Implementation
12.1
Application Information
12.2
Typical Application
12.2.1
Design Requirements
12.3
Initialization Setup
12.4
Power Supply Recommendations
12.4.1
Bulk Capacitance Sizing
12.5
Layout
12.5.1
Layout Guidelines
12.5.2
Layout Example
13
Device and Documentation Support
13.1
Receiving Notification of Documentation Updates
13.2
Support Resources
13.3
Trademarks
13.4
Electrostatic Discharge Caution
13.5
Glossary
14
Revision History
15
Mechanical, Packaging, and Orderable Information
15.1
Package Option Addendum
15.2
Tape and Reel Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGZ|48
MPQF123F
Thermal pad, mechanical data (Package|Pins)
Orderable Information
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Data Sheet
DRV8000-Q1
Automotive Highly-integrated, Multi-function Driver for Door Control
1
Features
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125°C, T
A
4.5V to 35V (40V abs. max) operating range
H-bridge or dual-channel half-bridge gate drivers
Smart gate drive architecture
Tripler charge pump for 100% PWM
Wide common mode current shunt amplifier
1 Integrated Half-bridge with I
OUT
Max 8A (R
DSON
= 132mΩ, 66mΩ per FET)
1 Integrated Half-bridge with I
OUT
Max 7A (R
DSON
= 160mΩ, 80mΩ per FET)
2 Integrated Half-bridges with I
OUT
Max 4A (R
DSON
= 400mΩ, 200mΩ per FET)
2 Integrated Half-bridges with I
OUT
Max 1.3A load (R
DSON
= 1500mΩ, 750mΩ per FET)
1 Configurable Integrated High-side driver as Lamp or LED driver with I
OUT
Max 1.5/0.5A (R
DSON
= 0.4/1.5Ω)
5 Integrated High-side drivers for 0.5/0.25A load (R
DSON
= 1.5Ω)
1 High-side driver to supply electro chromic (EC) glass MOSFET
1 external MOSFET gate driver for charge of electro chromic glass
1 integrated Low-side FET for discharge of electro chromic glass
Internal 10bit PWM generator for high-side drivers
All high-side drivers support a low- or high- current threshold constant current mode to drive a wide range of LED modules
1 external MOSFET gate driver for heater
Offline open load detection
V
DS
monitoring of low R
DSON
MOSFET for short circuit detection
Integrated driver output features Current regulation (ITRIP)
Muxable sense output (IPROPI)
Internal current sensing with proportional current output (IPROPI)
Advanced die temperature monitoring with multiple thermal clusters
Scaled supply voltage output
Protection and diagnostic features with configurable fault behavior
Load diagnostics in both the off-state and on-state to detect open load and short circuit
Over current and over temperature protection
Device Comparison Table
2
Applications
Door module
Body control modules
Zonal module