SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.3.2 Electro-chromic Driver Protection

The electro-chromic driver block has multiple protection and detection circuits for both charge and discharge states. There are the comparator-based detection circuits, protection circuits of OUT11 which are active during EC charge state (when configured with OUT11 as supply), and protection circuits on ECFB low-side discharge MOSFET.

EC supplied by OUT11: When the electrochrome drive is configured to be supplied by integrated high-side driver OUT11, the same protection and diagnostic functions as the other high-side drivers are available (e.g. during an overcurrent detection, the control loop is switched off). These high-side driver protections are active when the electrochrome is in the charge state (voltage ramp up). When in OUT11 EC mode ( OUT11_EC_MODE = 1b), OUT11 cannot be controlled in PWM mode.

Fault on OUT11 during EC charge: In case of an overtemperature shutdown fault (zone 3 or 4) or overcurrent fault on OUT11 while EC_ON = 1b (EC control enabled):

  • OUT11 is shut off (status register set)
  • DAC is reset (EC_V_TAR set to '00000')
  • ECDRV pin is pulled to ground
  • EC_ON remains '1'
  • ECFB_LS_EN remains as programmed

To restart EC control after OUT11 failure, the controller must read and clear the corresponding fault, and write the desired value to bits EC_V_TAR in register HS_EC_HEAT_CTRL.

If an open load is detected on OUT11 during EC charge, the OUT11_OLA bit in register HS_STAT is set.

Discharge Over current protection: If the load current into the ECFB pin LS MOSFET during discharge exceeds the over current threshold IOC_ECFB for longer than tDG_OC_ECFB, then the LS MOSFET is either Hi-Z (latch) or enters fixed-frequency regulation mode based on OUT7 ITRIP settings. The over current status bit ECFB_OC is set, and EC_HEAT is set. Overcurrent fault response is configurable with EC_FLT_MODE bit in register EC_CNFG. The ITRIP settings are shared with OUT7 ITRIP settings.

Table 7-19 Discharge Over Current Protection
EC_FLT_MODE Fault Response
0b Latch (Hi-Z)
1b ITRIP (OUT7 settings)

Discharge Open load detection: While discharging the EC, open-load can also be detected. Bit EC_OLEN in register EC_CNFG must be set. If the load current on ECFB is below IOL_ECFB_LS for longer than tDG_OL_ECFB_LS, then the open load status bit ECFB_OL is set, and WARN bit is set in register IC_STAT1.

For EC direct PVDD supply configuration, there are three comparator-based detection circuits that can be used when EC regulation is active in place of relying on the OUT11 protection and detection circuits. These include:

  • Short to Battery detection on ECFB (overvoltage)
  • Short to Ground detection on ECFB (undervoltage)
  • Open-load detection on ECFB

EC supply direct to PVDD: When the EC block is supplied directly to PVDD, short to battery, short to ground, and open load detection circuits can be independently enabled with bits ECFB_OV_MODE, ECFB_UV_MODE, and ECDRV_OL_EN in register EC_CNFG. These detection circuits can be enabled regardless of EC supply configuration if extra diagnostics are desired. However, if they are not desired then it is recommended to disable them in register.

DRV8000-Q1 Electrochrome with direct PVDD supply (OUT11 independent) Figure 7-10 Electrochrome with direct PVDD supply (OUT11 independent)

Short to Battery/OV detection: ECFB overvoltage or short to battery is detected when ECFB voltage exceeds PVDD - 1V, or threshold VECFB_OV, for longer than the deglitch time tECFB_OV_DG. BitECFB_OV_MODE determines the driver ECFB overvoltage fault response. The EC overvoltage deglitch time is configured with bit ECFB_OV_DG in register EC_CNFG.

For over voltage fault response control, bit ECFB_OV_MODE can be configured in register EC_CNFG. If ECFB_OV_MODE = 00b, then no action is taken during this fault. For ECFB_OV_MODE = 10b, when ECFB voltage exceeds ECFB_OV for longer than programmed deglitch time tECFB_OV_DG, then the ECFB_OV bit is set in EC_HEAT_ITRIP_STAT register, and EC_HEAT fault bit is set in register IC_STAT1. For ECFB_OV_MODE = 10b, when OV on ECFB occurs, the ECDRV pin is pulled down, and the ECFB LS FET is Hi-Z. Faults are reported in the same registers as for when ECFB_OV_MODE = 01b. The fault responses and bit values are summarized in the table below:

Table 7-20 Electrochrome Overvoltage Fault Response
ECFB_OV_MODE Fault Response
00b No action
01b Report fault in register
10b Pull-down ECDRV and ECFB LS FET, report fault in register
Table 7-21 EC Overvoltage Deglitch Times
ECFB_OV_DG Deglitch Time
00b 20 μs
01b 50 μs
10b 100 μs
11b 200 μs

Short to Ground/UV detection: ECFB under voltage or short to ground is detected when ECFB voltage is detected below the programmed threshold VECFB_UV_TH for longer than the programmed deglitch time tECFB_UV_DG. Bits ECFB_UV_TH and ECFB_UV_DG are set in register EC_CNFG.

Table 7-22 Electrochrome Undervoltage Thresholds
ECFB_UV_TH Under Voltage Threshold
0b 100 mV
1b 200 mV
Note: When the short to ground/under voltage detection is enabled, if the ECFB target voltage is set below the programmed threshold, which is either the lowest 4 or 8 bits of resolution depending on ECFB_UV_TH, a short to ground/under voltage will be detected. If it is desired to enable the short to ground/under voltage detection, these target voltage values should be avoided to prevent misdiagnosis of a short to ground/under voltage condition.

For under voltage fault response control, bit ECFB_UV_MODE can be configured in registerEC_CNFG. If ECFB_UV_MODE = 00b, then no action is taken when ECFB voltage falls below ECFB_UV. For ECFB_UV_MODE = 10b, then the ECFB_UV bit is set in EC_HEAT_ITRIP_STAT register, and EC_HEAT fault bit is set in register IC_STAT1. For ECFB_UV_MODE = 10b, when UV on ECFB occurs, the ECDRV pin is pulled down, and the ECFB LS FET is Hi-Z. Faults are reported in the same registers as for whenECFB_UV_MODE = 01b. The fault responses and bit values are summarized in the table below:

Table 7-23 Electrochrome Undervoltage Fault Response
ECFB_UV_MODE Fault Response
00b No action
01b Report fault in register
10b Pull-down ECDRV and ECFB LS FET, report fault in register
Table 7-24 EC Undervoltage Deglitch Times
ECFB_UV_DG Deglitch Time
00b 20 μs
01b 50 μs
10b 100 μs
11b 200 μs

PVDD supplied EC Open-load detection: If the EC block is not configured to be supplied with OUT11, a separate EC open-load detection circuit can be enabled with bit ECDRV_OL_EN in register EC_CNFG. When enabled, a current source injects a small current into the ECFB node, and the ECFB voltage is compared with the open-load threshold voltage. If the open-load threshold is exceeded, an open load condition is detected and the ECFB_OL bit will be set. The truth table below shows possible values for both open load and short to battery detection status:

Table 7-25 Open Load and Over Voltage Detection Truth Table
ECFB_OL ECFB_OV Status
1b 1b Short to battery/overvoltage
1b 0b Open-load
0b 1b Not possible
0b 0b Normal operation