SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.4.5.1.2 H-Bridge Control

In H-bridge control, both half-bridge gate drivers can be controlled as an H-bridge gate driver through a configurable combination of IN1 and IN2 input pins or the S_IN1 and S_IN2 bits in registerGD_HB_CTRL.

To set the control mode for the half-bridge gate drivers, the SPI BRG_MODE bit can be configured to either PH/EN or PWM control modes. The PH/EN mode allows for the H-bridge to be controlled with a speed/direction type of interface commanded by one PWM signal and one GPIO signal. The PWM mode allows for the H-bridge to be controlled with a more advanced scheme typically requiring two PWM signals. This allows the H-bridge driver to enter four different output states for additional control flexibility if required.

In PH/EN mode, each half-bridge input control modes are configured with bits INx_MODE in register GD_CNFG. By default, INx_MODE = 0b and both half-bridge are controlled from pins. If INx_MODE = 1b, the half-bridge is controlled with SPI bit S_INx. If IN1_MODE is set to 1b and IN2_MODE is set to 0b, the half-bridge 1 is controlled through SPI bit S_IN1, and half-bridge 2 is controlled with pin IN2. If both INx_MODE = 1b, then S_IN1 becomes EN and S_IN2 becomes PH, following pins IN1 and IN2.

The H-bridge freewheeling state is configurable through the BRG_FW register setting. In both the PH/EN and PWM modes the default active freewheeling mode is active low-side. This setting can be utilized to modify the bridge between low-side or high-side active freewheeling.

The H-bridge can be set to the Hi-Z state through the PWM or PH/EN control mode, using DRVOFF pin or S_HIZx bits. The S_HIZx bits are an OR when the gate driver is in PH/EN control mode, and puts both outputs SHx into high impedance.

Table 7-39 H-Bridge PH/EN Control (BRG_MODE = 01b, INx_MODE = 0b)
DRVOFF IN1 (EN) IN2 (PH) BRG_FW GH1 GL1 GH2 GL2 SH1 SH2 DESCRIPTION
1 X X X L L L L Z Z High Impedance
0 0 X 0b L H L H L L Low-Side Active Freewheel
0 0 X 1b H L H L H H High-Side Active Freewheel
0 1 0 X L H H L L H Drive SH2 → SH1 (Reverse)
0 1 1 X H L L H H L Drive SH1 → SH2 (Forward)
DRV8000-Q1 H-Bridge PH/EN Control Figure 7-20 H-Bridge PH/EN Control
Table 7-40 H-Bridge PH/EN Control (BRG_MODE = 01b, IN2_MODE = 1b)
DRVOFF IN1 (EN) S_IN2 (PH) BRG_FW GH1 GL1 GH2 GL2 SH1 SH2 DESCRIPTION
1 X X X L L L L Z Z High Impedance
0 0 X 0b L H L H L L Low-Side Active Freewheel
0 0 X 1b H L H L H H High-Side Active Freewheel
0 1 0b X L H H L L H Drive SH2 → SH1 (Reverse)
0 1 1b X H L L H H L Drive SH1 → SH2 (Forward)
DRV8000-Q1 H-Bridge PH/EN Mixed Control Figure 7-21 H-Bridge PH/EN Mixed Control
Table 7-41 H-Bridge PH/EN Control (BRG_MODE = 01b, IN1_MODE = 1b)
DRVOFF S_IN1 (EN) IN2 (PH) BRG_FW GH1 GL1 GH2 GL2 SH1 SH2 DESCRIPTION
1 X X X L L L L Z Z High Impedance
0 0 X 0b L H L H L L Low-Side Active Freewheel
0 0 X 1b H L H L H H High-Side Active Freewheel
0 1b 0 X L H H L L H Drive SH2 → SH1 (Reverse)
0 1b 1 X H L L H H L Drive SH1 → SH2 (Forward)
DRV8000-Q1 H-Bridge PH/EN Control (BRG_MODE = 01b, IN1_MODE = 1b) Figure 7-22 H-Bridge PH/EN Control (BRG_MODE = 01b, IN1_MODE = 1b)
Table 7-42 H-Bridge PWM Control (BRG_MODE = 10b)
DRVOFF IN1 IN2 BRG_FW GH1 GL1 GH2 GL2 SH1 SH2 DESCRIPTION
1 X X X L L L L Z Z High Impedance
0 0 0 X L L L L Z Z Diode Freewheel (Coast)
0 0 1 X L H H L L H Drive SH2 → SH1 (Reverse)
0 1 0 X H L L H H L Drive SH1 → SH2 (Forward)
0 1 1 0b L H L H L L Low-Side Active Freewheel
0 1 1 1b H L H L H H High-Side Active Freewheel
DRV8000-Q1 H-Bridge PWM Control Figure 7-23 H-Bridge PWM Control