SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin

The DRV8000-Q1 provides dedicated H-bridge gate driver disable function with the DRVOFF pin. The DRVOFF pin provides a direct hardware pin to shutdown the gate driver without relying on an SPI command or PWM input change. When DRVOFF is asserted, both gate driver half-bridges are Hi-Z by enabling the gate driver pull downs regardless of the other pin or SPI inputs. The integrated drivers and charge pump are independent from the DRVOFF pin.

The DRVOFF pin has a live status bit DRVOFF_STAT in regsiter GD_STAT that is continuously updated to reflect the status of the DRVOFF pin. This can be used to confirm that DRVOFF pin is either asserted or de-asserted.

Note: The host controller must assert DRVOFF for more than 3ms to register a valid DRVOFF command. To properly clear the DRVOFF status latch, a CLR_FLT must be issued after 3ms of DRVOFF going low. It is recommend the host check DRVOFF status DRVOFF_STAT bit in register GD_STAT before and after issue a CLR_FLT to confirm that DRVOFF status has cleared. If CLR_FLT is issued within 3ms of DRVOFF going low, DRVOFF status latch may not clear.

While DRVOFF is asserted, SPI communication and logic inputs are still available as long as DVDD is present.