Bypass the PVDD pin to the GND pin using a low-ESR ceramic bypass capacitor C_PVDD1. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to the GND pin. Additionally, bypass the PVDD pin using a bulk capacitor C_PVDD2 rated for PVDD. This component can be electrolytic. This capacitance must be at least 10 µF. It is acceptable if this capacitance is shared with the bulk capacitance for the external power MOSFETs.

Place a low-ESR ceramic capacitor C_FLY1 and C_FLY2 between the CPL1 / CPH1 and CPL2 / CP2H pins. Additionally, place a low-ESR ceramic capacitor C_VCP between the VCP and PVDD pins.

Additional bulk capacitance is required to bypass the high current path on the external power MOSFETs of the H-bridge driver. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.

For H-bridge driver external MOSFETs, bypass the drain pin to GND plane using a low-ESR ceramic bypass capacitor with appropriate voltage rating. Place this capacitor as close to the MOSFET drain and source pins as possible, with a thick trace or plane connection to GND plane. Place the series gate resistors as close to the MOSFET gate pins as possible.

For the current shunt amplifier, the placement of the sense resistor should be in line with the components of the power stage to minimize trace impedance. If possible, the shunt resistor should also be placed close to the connection to the CSA to decrease the possibility of coupling on other traces on the board.

For high-side current sense, the shunt resistor should be near the star point between the supply and the source of the high-side MOSFETs. For low-side current sense, the shunt resistor should be between the source of the low-side MOSFET and the star point ground connection of the power stage. The remaining components should be placed nearest to the device.

Routing of the sense signals should be done using a differential pair. In a differential pair, both signals are tightly coupled in the layout and the traces must run parallel from the shunt or sense resistor to the CSA at the input of the IC.

Bypass the DVDD pin to the DGND pin with C_DVDD. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the DGND pin. If local bypass capacitors are already present on these power supplies in close proximity of the device to minimize noise, these additional components for DVDD are not required.

For the EC driver, the both the C_ECDRV and C_ECFB bypass capacitors to GND should be placed as close to the respective pins as possible.

Do not connect the SL pin directly to the GND plane. Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.

Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the low-side MOSFET source back to the SL pin.