SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage PVDD –0.3 40 V
Power supply transient voltage ramp PVDD 2 V/µs
Digital Logic power supply voltage ramp DVDD 2 V/µs
Voltage difference between ground pins GND, PGND –0.3 0.3 V
Charge pump pin voltage VCP –0.3 PVDD + 15 V
Charge pump high-side pin voltage CP1H VPVDD – 0.3 VVCP + 0.3 V
Charge pump high-side pin voltage CP2H VPVDD – 0.6 VVCP + 0.3 V
Charge pump low-side pin voltage CP1L, CP2L –0.3 VPVDD + 0.3 V
Digital regulator pin voltage DVDD –0.3 5.75 V
Logic pin voltage GD_INx, PWM1, IPROPI/PWM2, DRVOFF nSLEEP, SCLK, SDI, nSCS –0.3 5.75 V
Output logic pin voltage SDO –0.3 VDVDD + 0.3 V
Output pin voltage OUT1-OUT12, ECDRV, ECFB –0.3 VPVDD + 0.9 V
Output current OUT1-OUT12, ECDRV, ECFB Internally Limited Internally Limited A
Heater and Electrochromic MOSFET gate drive pin voltage GH_HS, ECDRV VHEAT – 0.3 to VHEAT + 13 VVCP + 0.3 V
Heater and Electrochromic MOSFET source pin voltage SH_HS, ECFB –0.3 VPVDD + 0.3 V
High-side driver and Heater MOSFET source pin maximum energy dissipation, TJ = 25°C, LLOAD < 100 µH OUT7-OUT12, SH_HS - 1 mJ
High-side gate drive pin voltage GHx(2) –2 VVCP + 0.3 V
Transient 1-µs high-side gate drive pin voltage GHx(2) –5 VVCP + 0.3 V
High-side gate drive pin voltage with respect to SHx GHx(2) –0.3 13.5 V
High-side sense pin voltage SHx(2) –2 40 V
Transient 1-µs high-side sense pin voltage SHx(2) –5 40 V
Low-side gate drive pin voltage GLx(2) –2 13.5 V
Transient 1-µs low-side gate drive pin voltage GLx(2) –3 13.5 V
Low-side gate drive pin voltage with respect to PGND GLx(2) –0.3 13.5 V
Low-side snse pin voltage SL(2) –2 2 V
Transient 1-µs low-side sense pin voltage SL(2) –3 3 V
Gate drive current GHx, GLx Internally Limited Internally Limited A
Amplifier input pin voltage SN, SP –2 VVCP + 0.3 V
Transient 1-µs amplifier input pin voltage SN, SP –5 VVCP + 0.3 V
Amplifier input differential voltage SN, SP –5.75 5.75 V
Amplifier output pin voltage SO –0.3 VDVDD + 0.3 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) PVDD with respect to GHx, SHx, GLx, or SL should not exceed 40 V. When PVDD is greater than 35 V, negative voltage on GHx, SHx GLx, and SL should be limited to ensure this rating is not exceeded. When PVDD is less than 35 V, the full negative rating of GHx, SHx, GLx, and SL is available.