SLVSH22 May   2024 DRV8000-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUT7 HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Over Current Protection
          3. 7.4.2.2.3 High-side Driver Open Load Detection
      3. 7.4.3 Electro-chromic Glass Driver
        1. 7.4.3.1 Electro-chromic Driver Control
        2. 7.4.3.2 Electro-chromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 Half-bridge ITRIP Regulation
        3. 7.4.4.3 Half-bridge Protection and Diagnostics
          1. 7.4.4.3.1 Half-bridge Off-State Diagnostics (OLP)
          2. 7.4.4.3.2 Half-Bridge Active Open Load Detection (OLA)
          3. 7.4.4.3.3 Half-Bridge Over-Current Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
            1. 7.4.5.2.6.1 PDR Pre-Charge/Pre-Discharge Setup
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short Circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
  10. 9 DRV8000-Q1_STATUS Registers
  11. 10DRV8000-Q1_CNFG Registers
  12. 11DRV8000-Q1_CTRL Registers
  13. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
    3. 12.3 Initialization Setup
    4. 12.4 Power Supply Recommendations
      1. 12.4.1 Bulk Capacitance Sizing
    5. 12.5 Layout
      1. 12.5.1 Layout Guidelines
      2. 12.5.2 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Package Option Addendum
    2. 15.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

5 V ≤ VPVDD ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V and TJ = 25˚C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VCP, PVDD)
IPVDDQ PVDD sleep mode current VPVDD = 13.5 V, nSLEEP = 0 V -40 ≤ TJ ≤ 85˚C 2.5 5 µA
IDVDDQ DVDD sleep mode current VPVDD = 13.5 V, nSLEEP = 0 V -40 ≤ TJ ≤ 85˚C 2 4 µA
IPVDD PVDD active mode current VPVDD = 13.5, nSLEEP = 5 V 5 10 mA
IDVDD DVDD active mode current VDVDD = 5 V, SDO = 0 V 11.5 15 mA
IPVDD_CP_DIS PVDD charge pump disabled mode current VPVDD = 13.5 V, DIS_CP = 1, EN_GD = 0 V -40 ≤ TJ ≤ 85˚C 2 mA
IDVDD_CP_DIS DVDD charge pump disabled mode current VPVDD = 13.5 V, DIS_CP = 1, EN_GD = 0 V -40 ≤ TJ ≤ 85˚C 10 mA
tWAKE Turnon time nSLEEP = 5 V to active mode 1 ms
tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms
tDRVOFF_FLTR Filter time for DRVOFF signal asserted DRVOFF = 0 V to 5 V 15 µs
fVDD Digital oscillator switching frequency Primary frequency of spread spectrum 14.25 MHz
VVCP Charge pump regulator voltage with respect to PVDD VPVDD ≥ 9 V, IVCP ≤ 20 mA 9.5 10.5 11 V
VVCP Charge pump regulator voltage with respect to PVDD VPVDD = 7 V, IVCP ≤ 15 mA 8.5 9 11 V
VVCP Charge pump regulator voltage with respect to PVDD VPVDD = 5 V, IVCP ≤ 12 mA 6.8 7.5 11 V
IVCP_LIM Charge pump output current limit VPVDD = 13.5 V, CFLY1 = CFLY2 = 100 nF, CVCP = 1 µF, inrush during charge pump start-up 500 mA
fVCP Charge pump switching frequency Primary frequency of spread spectrum 400 kHz
LOGIC-LEVEL INPUTS (INx, nSLEEP, SCLK, SDI, etc)
VIL Input logic low voltage DRVOFF, GD_INx, PWM1, IPROPI/PWM2, nSLEEP, SCLK, SDI 0.3 VDVDD x 0.3 V
VIH Input logic high voltage DRVOFF, GD_INx, PWM1, IPROPI/PWM2, nSLEEP, SCLK, SDI VDVDD x 0.7 5.5 V
VHYS Input hysteresis DRVOFF, GD_INx, PWM1, IPROPI/PWM2, nSLEEP, SCLK, SDI VDVDD x 0.15 V
IIL Input logic low current VDIN = 0 V, DRVOFF, GD_INx, PWM1, IPROPI/PWM2, nSLEEP, SCLK, SDI –5 5 µA
IIL Input logic low current VDIN = 0 V, nSCS 25 50 µA
IIH Input logic high current VDIN = 5 V, nSCS –5 5 µA
IIH Input logic high current VDIN = 5 V, DRVOFF, GD_INx, PWM1, IPROPI/PWM2, nSLEEP, SCLK, SDI 25 50 µA
RPD Input pull-down resistance To GND, DRVOFF, GD_INx, PWM1, nSLEEP, SCLK, SDI 140 200 260 kΩ
RPU Input pull-up resistance To DVDD, nSCS 140 200 265 kΩ
PUSH-PULL OUTPUT SDO
VOL Output logic low voltage IOD = 5 mA 0.5 V
VOH Output logic high voltage IOD = –5 mA, SDO DVDD x 0.8 V
GATE DRIVERS (GHx, GLx, SHx, SL)
VGHx_L GHx low level output voltage IDRVN_HS = ISTRONG, IGHx = 1mA, GHx to SHx 0 0.25 V
VGLx_L GLx low level output voltage IDRVN_LS = ISTRONG, IGLx = 1mA, GLx to SL 0 0.25 V
VGHx_H GHx high level output voltage IDRVP_HS = IHOLD, IGHx = 1mA, VCP to GHx 0 0.25 V
VGLx_H GLx high level output voltage IDRVP_LS = IHOLD, IGLx = 1mA 10.5 V ≤ VPVDD ≤ 35 V, GLx to PGND 10.5 12.5 V
IDRVP Peak gate current (source) IDRVP_x = 0000b, VGSx = 3 V, VPVDD ≥ 7 V 0.2 0.5 0.83 mA
IDRVP_x = 0001b, VGSx = 3 V, VPVDD ≥ 7 V 0.5 1 1.6 mA
IDRVP_x = 0010b, VGSx = 3 V, VPVDD ≥ 7 V 1.3 2 2.8 mA
IDRVP_x = 0011b, VGSx = 3 V, VPVDD ≥ 7 V 2.1 3 4 mA
IDRVP_x = 0100b, VGSx = 3 V, VPVDD ≥ 7 V 2.9 4 5.3 mA
IDRVP_x = 0101b, VGSx = 3 V, VPVDD ≥ 7 V 3.75 5 6.4 mA
IDRVP_x = 0110b, VGSx = 3 V, VPVDD ≥ 7 V 4.5 6 7.6 mA
IDRVP_x = 0111b, VGSx = 3 V, VPVDD ≥ 7 V 5.5 7 9 mA
IDRVP_x = 1000b, VGSx = 3 V, VPVDD ≥ 7 V 6 8 10 mA
IDRVP_x = 1000b, VGSx = 3 V, VPVDD ≥ 7 V 9 12 15 mA
IDRVP_x = 1001b, VGSx = 3 V, VPVDD ≥ 7 V 12 16 20 mA
IDRVP_x = 1010b, VGSx = 3 V, VPVDD ≥ 7 V 15 20 25 mA
IDRVP_x = 1011b, VGSx = 3 V, VPVDD ≥ 7 V 18 24 30 mA
IDRVP_x = 1100b, VGSx = 3 V, VPVDD ≥ 7 V 24 31 40 mA
IDRVP_x = 1101b, VGSx = 3 V, VPVDD ≥ 7 V 28 48 62 mA
IDRVP_x = 1111b, VGSx = 3 V, VPVDD ≥ 7 V 46 62 78 mA
IDRVN Peak gate current (sink) IDRVN_x = 0000b, VGSx = 3 V, VPVDD ≥ 7 V 0.07 0.5 0.85 mA
IDRVN_x = 0001b, VGSx = 3 V, VPVDD ≥ 7 V 0.23 1 1.7 mA
IDRVN_x = 0010b, VGSx = 3 V, VPVDD ≥ 7 V 0.7 2 3.2 mA
IDRVN_x = 0011b, VGSx = 3 V, VPVDD ≥ 7 V 1.2 3 4.6 mA
IDRVN_x = 0100b, VGSx = 3 V, VPVDD ≥ 7 V 1.75 4 5.9 mA
IDRVN_x = 0101b, VGSx = 3 V, VPVDD ≥ 7 V 2.4 5 7.2 mA
IDRVN_x = 0110b, VGSx = 3 V, VPVDD ≥ 7 V 3 6 8.5 mA
IDRVN_x = 0111b, VGSx = 3 V, VPVDD ≥ 7 V 3.6 7 9.8 mA
IDRVN_x = 1000b, VGSx = 3 V, VPVDD ≥ 7 V 4.3 8 11 mA
IDRVN_x = 1001b, VGSx = 3 V, VPVDD ≥ 7 V 7.3 12 16 mA
IDRVN_x = 1010b, VGSx = 3 V, VPVDD ≥ 7 V 11 16 20 mA
IDRVN_x = 1011b, VGSx = 3 V, VPVDD ≥ 7 V 14.3 20 25 mA
IDRVN_x = 1100b, VGSx = 3 V, VPVDD ≥ 7 V 18 24 30 mA
IDRVN_x = 1101b, VGSx = 3 V, VPVDD ≥ 7 V 24 31 40 mA
IDRVN_x = 1110b, VGSx = 3 V, VPVDD ≥ 7 V 28 48 62 mA
IDRVN_x = 1111b, VGSx = 3 V, VPVDD ≥ 7 V 46 62 78 mA
IHOLD Gate pull-up hold current Gate hold source current, VGSx = 3 V 5 16 30 mA
ISTRONG Gate pull-down strong current VGSx = 3 V IDRV = 0.5 to 12 mA 30 62 100 mA
ISTRONG Gate pull-down strong current VGSx = 3 V IDRV = 16 to 62 mA 45 128 200 mA
RPDSA_LS Low-side semi-active gate pull-down GLx to SL, VGSx = 3 V 1.8 kΩ
RPDSA_LS Low-side semi-active gate pull-down GLx to SL, VGSx = 1 V 5 kΩ
RPD_HS High-side passive gate pull-down resistor GHx to SHx 150 kΩ
RPD_LS Low-side passive gate pull-down resistor GLx to SL 150 kΩ
ISHx Switch-node sense leakage current Into SHx, SHx = PVDD < 28 V GHx - SHx = 0 V, nSLEEP = 0 V –5 0 20 µA
ISHx Switch-node sense leakage current Into SHx, SHx = PVDD < 37 V GHx - SHx = 0 V, nSLEEP = 0 V –5 0 80 µA
ISHx Switch-node sense leakage current Into SHx, SHx = PVDD < 37 V GHx - SHx = 0 V, nSLEEP = 5 V –150 –100 0 µA
GATE DRIVER TIMINGS (GHx, GLx)
tPDR_LS Low-side rising propagation delay Input to GLx rising 300 850 ns
tPDF_LS Low-side falling propagation delay Input to GLx falling 300 600 ns
tPDR_HS High-side rising propagation delay Input to GHx rising 300 600 ns
tPDF_HS High-side falling propagation delay Input to GHx rising 300 600 ns
tDEAD Internal handshake dead-time GLx/GHx falling 10% to GHx/GLx rising 10% 350 ns
tDEAD_D Insertable digital dead-time VGS_TDEAD = 00b, Handshake only 0 µs
VGS_TDEAD = 01b 1.6 2 2.4 µs
VGS_TDEAD = 10b 3.4 4 4.6 µs
VGS_TDEAD = 11b 7.2 8 8.8 µs
CURRENT SHUNT AMPLIFIERS (SN, SO, SP)
VCOM Common mode input range –2 VPVDD + 2 V
GCSA Sense amplifier gain CSA_GAIN = 00b 9.75 10 10.25 V/V
CSA_GAIN = 01b 19.5 20 20.5 V/V
CSA_GAIN = 10b 39 40 41 V/V
CSA_GAIN = 11b 78 80 82 V/V
tSET Sense amplifier settling time to 1% VSO_STEP = 1.5 V, GCSA = 10 V/V CSO = 60 pF 2.2 µs
VSO_STEP = 1.5 V, GCSA = 20 V/V CSO = 60 pF 2.2 µs
VSO_STEP = 1.5 V, GCSA = 40 V/V CSO = 60 pF 2.2 µs
VSO_STEP = 1.5 V, GCSA = 80 V/V CSO = 60 pF 3 µs
tBLK_CSA Sense amplifier output blanking time CSA_BLK = 000b 0 %
CSA_BLK = 001b 25 %
CSA_BLK = 010b 37.5 %
CSA_BLK = 011b 50 %
CSA_BLK = 100b 62.5 %
CSA_BLK = 101b 75 %
CSA_BLK = 110b 87.5 %
CSA_BLK = 111b 100 %
tSLEW_CSA Output slew rate CSO = 60 pF 2.5 V/µs
VBIAS Output voltage bias VSPx = VSNx = 0 V, VDVDD = 3.3 V, CSA_DIV = 0b VDVDD / 2 V
VSPx = VSNx = 0 V, VDVDD = 3.3 V, CSA_DIV = 1b VDVDD / 8 V
VLINEAR Linear output voltage range VDVDD = 3.3 V = 5 V 0.25 VDVDD – 0.25 V
VOFF Input offset voltage VSPx = VSNx = 0V, TJ = 25˚C –1 1 mV
VOFF_D Input offset voltage drift VSPx = VSNx = 0 V ±10 ±25 µV/˚C
IBIAS Input bias current VSPx = VSNx = 0 V 100 µA
IBIAS_OFF Input bias current offset ISPx - ISNx 100 µA
CMRR Common mode rejection ratio DC, –40 ≤ TJ ≤ 125˚C 72 90 dB
DC, –40 ≤ TJ ≤ 150˚C 69 90 dB
20kHz 80 dB
PSRR Power supply rejection ratio PVDD to SOx, DC 100 dB
PVDD to SOx, 20kHz 90 dB
PVDD to SOx, 400kHz 70 dB
GATE DRIVER PROTECTION CIRCUITS
VCP_UV Charge pump undervoltage threshold VVCP - VPVDD, VVCP falling VCP_UV_MODE = 0b 4 4.75 5.5 V
VVCP - VPVDD, VVCP falling VCP_UV_MODE = 1b 5.5 6.25 7 V
tCP_UV_DG Charge pump undervoltage deglitch time 8 10 12.75 µs
VCP_SO Charge pump tripler to doubler switch over threshold VPVDD rising 18 18.75 19.5 V
VCP_SO Charge pump tripler to doubler switch over threshold VPVDD falling 17 17.75 18.5 V
tCP_SO_HYS Charge pump tripler to doubler switch over hysteresis 1 V
tCP_SO_DG Charge pump tripler to doubler switch over threshold deglitch 8 10 12.75 µs
VGS_CLP High-side driver VGS protection clamp 12.5 15 17 V
VGS_LVL Gate voltage monitor threshold VGHx – VSHx, VGLx – VPGND, VGS_LVL = 0b 1.1 1.4 1.75 V
VGHx – VSHx, VGLx – VPGND, VGS_LVL = 1b 0.75 1 1.2 V
tGS_FLT_DG VGS fault monitor deglitch time 1.5 2 2.75 µs
tGS_HS_DG VGS handshake monitor deglitch time 210 ns
tDRIVE VGS and VDS monitor blanking time VGS_TDRV = 000b 1.5 2 2.5 µs
VGS_TDRV = 001b 3.25 4 4.75 µs
VGS_TDRV = 010b 7.5 8 9 µs
VGS_TDRV = 011b 10 12 14 µs
VGS_TDRV = 100b 14 16 18 µs
VGS_TDRV = 101b 20 24 28 µs
VGS_TDRV = 110b 28 32 36 µs
VGS_TDRV = 111b 80 96 120 µs
VDS_LVL VDS overcurrent protection threshold VDS_LVL = 0000b 0.051 0.06 0.069 V
VDS_LVL = 0001b 0.068 0.08 0.092 V
VDS_LVL = 0010b 0.085 0.10 0.115 V
VDS_LVL = 0011b 0.102 0.12 0.138 V
VDS_LVL = 0100b 0.119 0.14 0.161 V
VDS_LVL = 0101b 0.136 0.16 0.184 V
VDS_LVL = 0110b 0.153 0.18 0.207 V
VDS_LVL = 0111b 0.17 0.2 0.23 V
VDS_LVL = 1000b 0.255 0.3 0.345 V
VDS_LVL = 1001b 0.35 0.4 0.45 V
VDS_LVL = 1010b 0.44 0.5 0.56 V
VDS_LVL = 1011b 0.52 0.6 0.68 V
VDS_LVL = 1100b 0.61 0.7 0.79 V
VDS_LVL = 1101b 0.88 1 1.12 V
VDS_LVL = 1110b 1.2 1.4 1.6 V
VDS_LVL = 1111b 1.75 2 2.25 V
tDS_DG VDS overcurrent protection deglitch time VDS_DG = 00b 0.75 1 1.5 µs
VDS_DG = 01b 1.5 2 2.5 µs
VDS_DG = 10b 3.25 4 4.75 µs
VDS_DG = 11b 7.5 8 9 µs
IOLD_PU Offline diagnostic current source Pull up current 3 mA
IOLD_PD Offline diagnostic current source Pull down current 3 mA
ROLD Offline open load resistance detection threshold VDS_LVL = 1.4 V, 4.9 V ≤ VPVDD ≤ 18 V 22 50 kΩ
VDS_LVL = 1.4 V, 4.9 V ≤ VPVDD ≤ 37 V 22 105 kΩ
VDS_LVL = 2 V, 4.9 V ≤ VPVDD ≤ 18 V 10 25 kΩ
VDS_LVL = 2 V, 4.9 V ≤ VPVDD ≤ 37 V 10 50 kΩ
HEATER MOSFET DRIVER
IGH_HS_HEAT Average charge-current TJ = 25 ˚C 50 mA
RGL_HEAT On-resistance (discharge stage) IGH_HS_HEAT = 25 mA; TJ = 25 ˚C 15 20 25 Ω
RGL_HEAT On-resistance (discharge stage) IGH_HS_HEAT = 25 mA; TJ = 125 ˚C 28 36 Ω
VGH_HS_HIGH GH_HS high level output voltage VPVDD = 4.5 V; ICP = 15 mA VSH_HS + 6 V
VGH_HS_HIGH GH_HS high level output voltage VPVDD = 13.5 V; ICP = 15 mA VSH_HS + 8 VSH_HS + 10 VSH_HS + 11.5 V
IHEAT_SH_STBY_LK SH_HS leakage current standby 25 µA
RGS_HEAT Passive gate-clamp resistance 150 kΩ
tPDR_GH_HS GH_HS rising propagation delay  VPVDD = 13.5 V; RG = 0 Ω; CG = 2.7 nF 0.5 µs
tPDF_GH_HS GH_HS falling propagation delay VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 0.5 µs
tRISE_GH_HS Rise time (switch mode) VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 300 ns
tFALL_GH_HS Fall time (switch mode) VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 170 ns
HEATER PROTECTION CIRCUITS
VDS_LVL_HEAT VDS overcurrent protection threshold for heater MOSFET HEAT_VDS_LVL = 0000b 0.051 0.06 0.069 V
HEAT_VDS_LVL = 0001b 0.068 0.08 0.092 V
HEAT_VDS_LVL = 0010b 0.085 0.10 0.115 V
HEAT_VDS_LVL = 0011b 0.102 0.12 0.138 V
HEAT_VDS_LVL = 0100b 0.119 0.14 0.161 V
HEAT_VDS_LVL = 0101b 0.136 0.16 0.184 V
HEAT_VDS_LVL = 0110b 0.153 0.18 0.207 V
HEAT_VDS_LVL = 0111b 0.17 0.2 0.23 V
HEAT_VDS_LVL = 1000b 0.204 0.240 0.276 V
HEAT_VDS_LVL = 1001b 0.238 0.280 0.322 V
HEAT_VDS_LVL = 1010b 0.272 0.320 0.368 V
HEAT_VDS_LVL = 1011b 0.306 0.360 0.414 V
HEAT_VDS_LVL = 1100b 0.340 0.400 0.460 V
HEAT_VDS_LVL = 1101b 0.374 0.440 0.506 V
HEAT_VDS_LVL = 1110b 0.476 0.560 0.644 V
HEAT_VDS_LVL = 1111b 0.85 1 1.15 V
tDS_HEAT_DG VDS overcurrent protection deglitch time HEAT_VDS_DG = 00b 0.75 1 1.5 µs
HEAT_VDS_DG = 01b 1.5 2 2.5 µs
HEAT_VDS_DG = 10b 3.25 4 4.75 µs
HEAT_VDS_DG = 11b 7.5 8 9 µs
tDS_HEAT_BLK VDS overcurrent protection blanking time HEAT_VDS_BLK = 00b 3.25 4 4.75 µs
HEAT_VDS_BLK = 01b 7.5 8 9 µs
HEAT_VDS_BLK = 10b 14 16 18 µs
HEAT_VDS_BLK = 11b 28 32 36 µs
VOL_HEAT Open load threshold voltage VSLx = 0 V 1.8 2 2.2 V
IOL_HEAT Pull-up current source open-load diagnosis activated VSLx = 0 V; VSHheater = 4.5 V 1 mA
tOL_HEAT Open-load filter time for heater MOSFET 2 ms
ELECTROCHROMIC DRIVER
RDSON ECFB Low-side MOSFET on resistance for EC discharge VPVDD = 13.5 V; TJ = 25 ˚C; IECFB = ±0.5 A
ECFB_LS_EN = 1b		 1500 mΩ
RDSON ECFB Low-side MOSFET on resistance for EC discharge VPVDD = 13.5 V; TJ = 150 ˚C; IECFB = ±0.5 A
ECFB_LS_EN = 1b		 3000 mΩ
IOC_ECFB Output current threshold of low-side MOSFET VPVDD = 13.5 V; TJ = 25 ˚C; IECFB current sink 0.5 1 A
tDG_OC_ECFB Over current shutdown deglitch time VPVDD = 13.5 V; TJ = 25 ˚C; IECFB current sink 10 50 µs
dVECFB/dt Slew rate of ECFB, low-side MOSFET VPVDD = 13.5 V, VDVDD = 5 V, Rload = 64 Ω 7 V/µs
IOL_ECFB_LS Open load detection threshold for EC during discharge EC_OLEN = 1b, ECFB_LS_EN = 1b 10 20 30 mA
tDG_OL_ECFB_LS Open load detection deglitch time EC_OLEN = 1b, ECFB_LS_EN = 1b 400 600 µs
IOL_PU_ECFB ECFB Open load pull-up current source, OUT11 independent mode OUT11_EC_MODE = 0b, ECDRV_OL_EN = 1b, EC_ON = 1b 200 µA
VEC_CTRLmax Maximum EC-control voltage target for ECFB ECFB_MAX = 1b 1.4 1.6 V
VEC_CTRLmax Maximum EC-control voltage target for ECFB ECFB_MAX = 0b 1.12 1.28 V
VEC_res Minimum resolution for adjustable voltage of ECFB EC_ON = 1b 23.8 mV
DNLECFB Differential Non Linearity EC_ON = 1b –2 2 LSB
|dVECFB| Voltage deviation between target and ECFB Vtarget = 1.5V, dVECFB=Vtarget - VECFB; |IECDRV| < 1 µA –5% (–1LSB) +5% (+1LSB) mV
|dVECFB| Voltage deviation between target and ECFB Vtarget = 23.8 mV, dVECFB=Vtarget - VECFB; |IECDRV| < 1 µA –5% (–1LSB) +5% (+1LSB) mV
VECFB_HI Indicates voltage at ECFB is higher than target EC_ON = 1b Vtarget + 0.12 V
VECFB_LO Indicates voltage at ECFB is lower than target EC_ON = 1b Vtarget – 0.12 V
tFT_ECFB Filter time of ECFB high/low flag EC_ON = 1b 32 µs
tBLK_ECFB Blanking time of EC regulation flags Any EC target voltage change 200 250 300 µs
VECFB_UV Threshold for undervoltage on ECFB ECFB_UV_MODE = 01b or 10b, EC_ON = 1b, ECFB_UV_TH = 0b 75 100 125 mV
ECFB_UV_MODE = 01b or 10b, EC_ON = 1b, ECFB_UV_TH = 1b 170 200 230 mV
tECFB_UV_DG Deglitch time for undervoltage flag on ECFB ECFB_UV_MODE = 01b or 10b, ECFB_UV_DG = 00b 16 20 24 µs
ECFB_UV_MODE = 01b or 10b, ECFB_UV_DG = 01b 40 50 60 µs
ECFB_UV_MODE = 01b or 10b, ECFB_UV_DG = 10b 80 100 120 µs
ECFB_UV_MODE = 01b or 10b, ECFB_UV_DG = 11b 160 200 240 µs
VECFB_OV Threshold for overvoltage on ECFB ECFB_OV_MODE = 01b or 10b, EC_ON = 1b VPVDD – 1V V
tECFB_OV_DG Deglitch time for overvoltage flag on ECFB ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 00b 16 20 24 µs
ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 01b 40 50 60 µs
ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 10b 80 100 120 µs
ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 11b 160 200 240 µs
VECDRVminHIGH Output voltage range of ECDRV when EC_ON = 1 IECDRV = -10µA 4.2 6 V
VECDRVmaxLOW Output voltage range of ECDRV when EC_ON = 0 IECDRV = 10µA 0 0.7 V
IECDRV Current into ECDRV Vtarget > VECFB + 500 mV;
VECDRV = 3.5 V		 –700 –80 µA
IECDRV Current into ECDRV Vtarget < VECFB - 500 mV;
VECDRV = 1.0 V;
Vtarget = 0 V; VECFB = 0.5 V		 150 350 µA
RECDRV_DIS Pull-down resistance at ECDRV in fast discharge mode VECDRV = 0.7 V; EC enabled, then EC<5:0> = 0 or EC disabled 11 kΩ
tDISCHARGE Auto-discharge pulse width ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 240 300 360 ms
tECFB_DISC_BLK Auto-discharge blanking time ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 2.25 3 3.75 ms
VDISC_TH PWM discharge level VECDRV ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 350 400 450 mV
VDISC_TH_DIFF PWM discharge threshold level VECDRV - VECFB ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b –50 0 50 mV
HALF-BRIDGE DRIVERS
RON_OUT1,2_HS High-side MOSFET on resistance IOUT = 1 A, TJ = 25 ˚C 750 mΩ
IOUT = 0.5 A, TJ = 150 ˚C 1425 mΩ
RON_OUT1,2_LS Low-side MOSFET on resistance IOUT = 1 A, TJ = 25 ˚C 750 mΩ
IOUT = 0.5 A, TJ = 150 ˚C 1425 mΩ
RON_OUT3,4_HS High-side MOSFET on resistance IOUT = 4 A, TJ = 25 ˚C 200 mΩ
IOUT = 2 A, TJ = 150 ˚C 400 mΩ
RON_OUT3,4_LS Low-side MOSFET on resistance IOUT = 4 A, TJ = 25 ˚C 200 mΩ
IOUT = 2 A, TJ = 150 ˚C 400 mΩ
RON_OUT5_HS High-side MOSFET on resistance IOUT = 7 A, TJ = 25 ˚C 66 mΩ
IOUT = 3.5 A, TJ = 150 ˚C 132 mΩ
RON_OUT5_LS Low-side MOSFET on resistance IOUT = 7.5 A, TJ = 25 ˚C 66 mΩ
IOUT = 3.5 A, TJ = 150 ˚C 132 mΩ
RON_OUT6_HS High-side MOSFET on resistance IOUT = 8 A, TJ = 25 ˚C 80 mΩ
RON_OUT6_HS High-side MOSFET on resistance IOUT = 4 A, TJ = 150 ˚C 160 mΩ
RON_OUT6_LS Low-side MOSFET on resistance IOUT = 8 A, TJ = 25 ˚C 80 mΩ
RON_OUT6_LS Low-side MOSFET on resistance IOUT = 4 A, TJ = 150 ˚C 160 mΩ
SROUT_HB Output voltage rise/fall time for all half-bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 00b 1.6 V/µs
SROUT_HB Output voltage rise/fall time for all half-bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 01b 13.5 V/µs
SROUT_HB Output voltage rise/fall time for all half-bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 10b 24 V/µs
tPD_OUT_HB_HS_R Propagation time during output voltage rise for HS ON command or INx (SPI last transition) to OUTx 10% voltage rise (any SR setting) 1.8 8.7 µs
tPD_OUT_HB_HS_F Propagation time during output voltage fall for HS ON command or INx (SPI last transition) to OUTx 10% voltage fall  (any SR setting) 1.2 9.2 µs
tPD_OUT_HB_LS_R Propagation time during output voltage rise for LS ON command or INx (SPI last transition) to OUTx 10% voltage rise  (any SR setting) 1.5 8 µs
tPD_OUT_HB_LS_F Propagation time during output voltage fall for LS ON command or INx (SPI last transition) to OUTx 10% voltage fall  (any SR setting) 1.4 8 µs
tDEAD_HS_ON Dead time during output voltage rise for HS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1.3 4.7 µs
tDEAD_HS_OFF Dead time during output voltage fall for HS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1.1 4.8 µs
tDEAD_LS_ON Dead time during output voltage rise for LS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1.4 5.8 µs
tDEAD_LS_OFF Dead time during output voltage fall for LS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1.7 14 µs
HALF-BRIDGE PROTECTION CIRCUITS
IOCP_OUT1,2 Over-current protection threshold 1.3 2 A
IOCP_OUT3,4 Over-current protection threshold 4 8 A
IOCP_OUT5 Over-current protection threshold 8 16 A
IOCP_OUT6 Over-current protection threshold 7 13 A
tDG_OCP_HB Overcurrent protection deglitch time in half-bridge drivers(1)(2) OUTX_OCP_DG = 00b 4.5 6 7.3 µs
OUTX_OCP_DG = 01b 8 10 12 µs
OUTX_OCP_DG = 10b 16 20 24 µs
OUTX_OCP_DG = 11b 48 60 72 µs
IITRIP_OUT1,2 Current threshold to trigger ITRIP regulation for OUT1 and OUT2 OUT1_ITRIP_LVL = 1b and OUT2_ITRIP_LVL = 1b 0.75 1 A
OUT1_ITRIP_LVL = 0b and OUT2_ITRIP_LVL = 0b 0.60 0.8 A
IITRIP_OUT3,4 Current threshold to trigger ITRIP regulation for OUT3 and OUT4 OUT3_ITRIP_LVL = 10b and OUT4_ITRIP_LVL = 10b 3 4 A
OUT3_ITRIP_LVL = 01b and OUT4_ITRIP_LVL = 01b 1.7 3.15 A
OUT3_ITRIP_LVL = 00b and OUT4_ITRIP_LVL = 00b 1.1 1.5 A
IITRIP_OUT5 Current threshold to trigger ITRIP regulation for OUT5 OUT5_ITRIP_LVL = 10b 6.6 8.7 A
OUT5_ITRIP_LVL = 01b 5.6 7.5 A
OUT5_ITRIP_LVL = 00b 2.5 3.1 A
IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 10b 5.5 7.1 A
IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 01b 4.7 6.1 A
IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 00b 1.9 2.6 A
fITRIP_HB Fixed frequency of ITRIP regulation for half-bridge drivers OUTX_ITRIP_FREQ = 00b 18 20 22 kHz
OUTX_ITRIP_FREQ = 01b 9 10 11 kHz
OUTX_ITRIP_FREQ = 10b 4 5 6 kHz
OUTX_ITRIP_FREQ = 11b 2 2.5 3 kHz
tDG_ITRIP_HB ITRIP regulation deglitch time for half-bridge drivers OUTX_ITRIP_DG = 00b 1.5 2 2.5 µs
OUTX_ITRIP_DG = 01b 4.5 5 5.5 µs
OUTX_ITRIP_DG = 10b 8 10 12 µs
OUTX_ITRIP_DG = 11b 16 20 24 µs
IOLA_OUT1,2 Under-current threshold for half-bridges 1 and 2 6 20 30 mA
IOLA_OUT3,4 Under-current threshold for half-bridges 3 and 4 15 50 90 mA
IOLA_OUT5 Under-current threshold for half-bridges 5 40 150 300 mA
IOLA_OUT6 Under-current threshold for half-bridges 6 30 120 240 mA
tOLA_HB Filter time of open-load signal for half-bridges Duration of open-load condition to set the status bit 4 ms
AIPROPI1,2 Current scaling factor for OUT1-2 500 A/A
AIPROPI3,4 Current scaling factor for OUT3-4 2000 A/A
AIPROPI5,6 Current scaling factor for OUT5-6 6000 A/A
IACC_1,2 Current sense output accuracy for low current OUT1-2 0.1 A < IOUT1,2 < 1 A -7 7 %
IACC_3,4_LOW Current sense output accuracy for low current OUT3-4 0.1 A < IOUT3,4 < 0.8 A -10 10 %
IACC_3,4_HI Current sense output accuracy for high current OUT3-4 0.8 A < IOUT3,4 < 4 A -8 8 %
IACC_5_LOW Current sense output accuracy for low current OUT5 0.1 A < IOUT5 < 0.8 A -30 30 %
IACC_5_HI Current sense output accuracy for high current OUT5 0.8 A < IOUT5 < 8 A -7 7 %
IACC_6_LOW Current sense output error for low current OUT6 0.1 A < IOUT6 < 0.8 A -30 30 %
IACC_6_HI Current sense output accuracy for high current OUT6 0.8 A < IOUT6 < 8 A -7 7 %
RS_GND Resistance on OUTx to GND that will be detected as short during OLP VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1 kΩ
RS_PVDD Resistance on OUTx to PVDD that will be detected as short during OLP VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1 kΩ
ROPEN_HB Resistance on OUTx that will be detected as open VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1.5 kΩ
VOLP_REFH OLP comparator Reference High OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b
 		 2.65 V
VOLP_REFL OLP comparator Reference Low OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b
 		 2 V
ROLP_PU Internal pull-up resistance on OUTx to VDD during OLP OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b
 		 1 kΩ
ROLP_PD Internal pull-down resistance on OUTx to VDD during OLP OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b
 		 1 kΩ
HIGH-SIDE DRIVERS
RDSON OUT7 (low RDSON mode) High-side MOSFET on resistance in low resistance mode TJ = 25 ˚C; IOUT7 = ±0.5 A 400 mΩ
TJ = 150 ˚C; IOUT7 = ±0.25 A 800 mΩ
RDSON OUT7 (high RDSON mode) High-side MOSFET on resistance in high resistance mode TJ = 25 ˚C; IOUT7 = ±0.5 A 1500 mΩ
TJ = 150 ˚C; IOUT7 = ±0.25 A 2800 mΩ
RDSON OUT8 High-side MOSFET on resistance TJ = 25 ˚C; IOUT8 = ±0.25 A 1500 mΩ
TJ  = 150 ˚C; IOUT8 = ±0.125 A 2800 mΩ
RDSON OUT9 High-side MOSFET on resistance TJ = 25 ˚C; IOUT9 = ±0.25 A 1500 mΩ
TJ = 150 ˚C; IOUT9 = ±0.125 A 2800 mΩ
RDSON OUT10 High-side MOSFET on resistance TJ = 25 ˚C; IOUT10 = ±0.25 A 1500 mΩ
TJ = 150 ˚C; IOUT10 = ±0.125 A 2800 mΩ
RDSON OUT11 High-side MOSFET on resistance TJ = 25 ˚C; IOUT11 = ±0.25 A 1500 mΩ
TJ = 150 ˚C; IOUT11 = ±0.125 A 2800 mΩ
RDSON OUT12 High-side MOSFET on resistance TJ = 25 ˚C; IOUT12 = ±0.25 A 1500 mΩ
TJ = 150 ˚C; IOUT12 = ±0.125 A 2800 mΩ
SRHS_OUT7_HI Slew rate for OUT7 High RDSON mode OUT7_RDSON_MODE = 0b, 10 to 90% 0.35 V/µs
SRHS_OUT7_LO Slew rate for OUT7 Low RDSON mode OUT7_RDSON_MODE = 1b, 10 to 90% 0.29 V/µs
SRHS Slew rate for OUT8 – OUT12 10 to 90% 1.54 V/µs
tPD_OUT7_HI Propagation delay time driver for OUT7 High RDSON mode High-side ON command (SPI last transition) to OUT7 transition from Hi-Z state 16 µs
tPD_OUT7_LO Propagation delay time driver for OUT7 Low RDSON mode High-side ON command (SPI last transition) to OUT7 transition from Hi-Z state 19 µs
tPD_HS Propagation delay time driver for high-side drivers OUT8 – OUT12 High-side OFF command (SPI last transition) to OUTx transition from ON state 2 µs
fPWMx(00) PWM switching frequency PWM_OUTX_FREQ = 00b 78 108 138 Hz
fPWMx(01) PWM switching frequency PWM_OUTX_FREQ = 01b 157 217 277 Hz
fPWMx(10) PWM switching frequency PWM_OUTX_FREQ = 10b 229 289 359 Hz
ILEAK_H Switched-off output current high-side drivers of OUT7-12 VOUT = 0 V; standby mode –10 µA
HIGH-SIDE DRIVER PROTECTION CIRCUITS
IOC7 Over current threshold in high RDSON mode OUT7_RDSON_MODE = 0b 500 1000 mA
Over current threshold in low RDSON mode OUT7_RDSON_MODE = 1b 1500 3000 mA
IOC8, IOC9, IOC10, IOC11,IOC12 Over current threshold OUT8 - OUT12 OUTX_OC_TH = 0b 250 500 mA
IOC8, IOC9, IOC10, IOC11,IOC12 Over current threshold OUT8 - OUT12 OUTX_OC_TH = 1b 500 1000 mA
ICCM_OUT7 Constant current level for high-side driver OUT7 High RDSON OUT7_RDSON_MODE = 0b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 0b 100 175 mA
ICCM_OUT7 Constant current level for high-side driver OUT7 High RDSON OUT7_RDSON_MODE = 0b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 1b 200 350 mA
ICCM Constant current level for high-side drivers OUTX_CCM_EN = 1b, OUTX_CCM_TO = 0b 100 175 mA
OUTX_CCM_EN = 1b, OUTX_CCM_TO = 1b 200 350 mA
tCCMto Constant current mode time expiration OUTX_CCM_EN = 1b, OUTX_CCM_TO = 0b 16 20 24 ms
OUTX_CCM_EN = 1b, OUTX_CCM_TO = 1b 8 10 12 ms
tOCP_HS_DG Overcurrent protection deglitch time in high side drivers(1)(2) OUTX_OCP_DG = 00b 4.5 6 7.3 µs
OUTX_OCP_DG = 01b 8 10 12 µs
OUTX_OCP_DG = 10b 16 20 24 µs
OUTX_OCP_DG = 11b 48 60 72 µs
tITRIP_HS_BLK Blanking time of OUT7 ITRIP OUT_ITRIP_BLK = 01b 0 µs
OUT_ITRIP_BLK = 10b 16 20 24 µs
OUT_ITRIP_BLK = 11b 32 40 48 µs
tITRIP_HS_DG ITRIP filter time for high-side driver OUT7 OUT7_ITRIP_DG = 00b 39 48 59 µs
OUT7_ITRIP_DG = 01b 32 40 48 µs
OUT7_ITRIP_DG = 10b 26 32 38 µs
OUT7_ITRIP_DG = 11b 19 24 29 µs
fITRIP_HS ITRIP frequency for high-side driver OUT7 OUT7_ITRIP_FREQ = 00b 1.7 kHz
OUT7_ITRIP_FREQ = 01b 2.2 kHz
OUT7_ITRIP_FREQ = 10b 3 kHz
OUT7_ITRIP_FREQ = 11b 4.4 kHz
IOLD7 Open-load threshold for OUT7 OUT7_RDSON_MODE = 1b 15 30 mA
Open-load threshold for OUT7 OUT7_RDSON_MODE = 0b 5 10 mA
IOLD8, IOLD9, IOLD10, IOLD11, IOLD12 Open-load threshold for OUT8 - OUT12 OUTX_OLA_TH = 0b 1.5 3 mA
OUTX_OLA_TH = 1b 4 12 mA
tOLD_HS Filter time of open-load signal for high-side drivers Duration of open-load condition to set the status bit 200 250 µs
AIPROPI7_LO Current scaling factor for OUT7 in low on-resistance mode OUT7_RDSON_MODE = 1b 1500 A/A
AIPROPI7_HI Current scaling factor for OUT7 in high on-resistance mode OUT7_RDSON_MODE = 0b 750 A/A
AIPROPI8, AIPROPI9, AIPROPI10, AIPROPI11, AIPROPI12,  Current scaling factor for OUT8-12 750 A/A
IACC_7_HI_RDSON Current sense output accuracy for OUT7 in high RDSON mode 0.1 A < IOUT7 < 0.5 A -18 18 %
IACC_7_LOW_RDSON Current sense output accuracy for OUT7 in low RDSON mode 0.5 A < IOUT7 < 1.5 A -14 14 %
IACC_8-12_LO Current sense output accuracy for low current OUT8-12 0.05 A < IOUT8-12 < 0.1 A -28 28 %
IACC_8-12_HI Current sense output accuracy for high current OUT8-12 0.1 A < IOUT8-12 < 0.5 A -18 18 %
tIPROPI_BLK IPROPI blanking time 32 µs
PROTECTION CIRCUITS
VPVDD_UV PVDD undervoltage threshold VPVDD rising 4.425 4.725 5 V
VPVDD falling 4.225 4.525 4.8 V
VPVDD_UV_HYS PVDD undervoltage hysteresis Rising to falling threshold 200 mV
tPVDD_UV_DG PVDD undervoltage deglitch time 8 10 12.75 µs
VPVDD_OV PVDD overvoltage threshold VPVDD rising, PVDD_OV_LVL = 0b 21 22 23 V
VPVDD falling, PVDD_OV_LVL = 0b 20 21 22 V
VPVDD rising, PVDD_OV_LVL = 1b 27 28 29 V
VPVDD falling, PVDD_OV_LVL = 1b 26 27 28 V
VPVDD_OV_HYS PVDD overvoltage hysteresis Rising to falling threshold 1 V
tPVDD_OV_DG PVDD overvoltage deglitch time PVDD_OV_DG = 00b 0.75 1 1.5 µs
PVDD_OV_DG = 01b 1.5 2 2.5 µs
PVDD_OV_DG = 10b 3.25 4 4.75 µs
PVDD_OV_DG = 11b 7 8 9 µs
VDVDD_POR DVDD supply POR threshold DVDD falling 2.5 2.7 2.9 V
DVDD rising 2.6 2.8 3 V
VDVDD_POR_HYS DVDD POR hysteresis Rising to falling threshold 100 mV
tDVDD_POR_DG DVDD POR deglitch time 5 12 25 µs
tWD Watchdog timer period WD_WIN = 0b 36 40 44 ms
WD_WIN = 1b 90 100 110 ms
AIPROPI_PVDD_VOUT IPROPI PVDD Voltage Sense Output Scaling Factor 30 32 34 V/V
VIPROPI_TEMP_VOUT IPROPI Temperature Sense Output –17 +17 °C
TOTW1 Low Thermal warning temperature TJ rising 100 115 130 °C
TOTW2 High Thermal warning temperature TJ rising 125 140 155 °C
THYS Thermal warning hysteresis 20 °C
TOTSD Thermal shutdown temperature TJ rising 155 170 185 °C
THYS Thermal shutdown hysteresis 20 °C
tOTSD_DG Thermal shutdown deglitch time 10 µs
(1) For 20 V < VPVDD < 28 V, the OCP deglicth time must be limited to up to 20 µs (OUTX_HB_OCP_DEG or OUTX_HS_OCP_DEG = 10b).
(2) For VPVDD > 28 V, the OCP deglicth time must be limited to 6 µs (Lowest Deglitch Value, (OUTX_HB_OCP_DEG or OUTX_HS_OCP_DEG = 00b).