SLVSH58 August   2024 DRV81004-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
      1. 5.5.1 SPI Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Control Pins
        1. 6.3.1.1 Input Pins
        2. 6.3.1.2 nSLEEP Pin
      2. 6.3.2 Power Supply
        1. 6.3.2.1 Modes of Operation
          1. 6.3.2.1.1 Power-up
          2. 6.3.2.1.2 Sleep mode
          3. 6.3.2.1.3 Idle mode
          4. 6.3.2.1.4 Active mode
          5. 6.3.2.1.5 Limp Home mode
          6. 6.3.2.1.6 Reset condition
      3. 6.3.3 Power Stage
        1. 6.3.3.1 Switching Resistive Loads
        2. 6.3.3.2 Inductive Output Clamp
        3. 6.3.3.3 Maximum Load Inductance
        4. 6.3.3.4 Switching Channels in parallel
      4. 6.3.4 Protection and Diagnostics
        1. 6.3.4.1 Undervoltage on VM
        2. 6.3.4.2 Overcurrent Protection
        3. 6.3.4.3 Over Temperature Protection
        4. 6.3.4.4 Over Temperature Warning
        5. 6.3.4.5 Over Temperature and Overcurrent Protection in Limp Home mode
        6. 6.3.4.6 Reverse Polarity Protection
        7. 6.3.4.7 Over Voltage Protection
        8. 6.3.4.8 Output Status Monitor
      5. 6.3.5 SPI Communication
        1. 6.3.5.1 SPI Signal Description
          1. 6.3.5.1.1 Chip Select (nSCS)
            1. 6.3.5.1.1.1 Logic high to logic low Transition
            2. 6.3.5.1.1.2 Logic low to logic high Transition
          2. 6.3.5.1.2 Serial Clock (SCLK)
          3. 6.3.5.1.3 Serial Input (SDI)
          4. 6.3.5.1.4 Serial Output (SDO)
        2. 6.3.5.2 Daisy Chain Capability
        3. 6.3.5.3 SPI Protocol
        4. 6.3.5.4 SPI Registers
          1. 6.3.5.4.1  Standard Diagnosis Register
          2. 6.3.5.4.2  Output control register
          3. 6.3.5.4.3  Input 0 Mapping Register
          4. 6.3.5.4.4  Input 1 Mapping Register
          5. 6.3.5.4.5  Input Status Monitor Register
          6. 6.3.5.4.6  Open Load Current Control Register
          7. 6.3.5.4.7  Output Status Monitor Register
          8. 6.3.5.4.8  Configuration Register
          9. 6.3.5.4.9  Output Clear Latch Register
          10. 6.3.5.4.10 Configuration Register 2
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Typical Application
      2. 7.1.2 Suggested External Components
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Package Footprint Compatibility
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5.3 SPI Protocol

The relationship between SDI and SDO content during SPI communication is shown in Figure 6-15. SDI line represents the frame sent from the microcontroller and SDO line is the answer provided by DRV81004-Q1.

DRV81004-Q1 Relationship between SDI and SDO during SPI communicationFigure 6-15 Relationship between SDI and SDO during SPI communication

The SPI protocol provides the answer to a command frame only with the next transmission triggered by the microcontroller. Although the biggest majority of commands and frames implemented in DRV81004-Q1 can be decoded without the knowledge of what happened before, it is advisable to consider what the microcontroller sent in the previous transmission to decode DRV81004-Q1 response frame completely. The sequence of commands to read and write the content of a register looks as follows:

DRV81004-Q1 Register content sent back to microcontrollerFigure 6-16 Register content sent back to microcontroller

There are 3 special situations where the frame sent back to the microcontroller is not related directly to the previous received frame:

  • In case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8 with a minimum of 16 bits), shown below.

  • When DRV81004-Q1 logic supply comes out of Power-On reset condition or after a Software Reset, as shown below.

  • In case of command syntax errors

    • write command starting with 11b instead of 10b

    • read command starting with 00b instead of 01b

    • read or write commands on registers which are reserved or not used

DRV81004-Q1 Response after a error in transmissionFigure 6-17 Response after a error in transmission
DRV81004-Q1 Response after coming out of Power-On reset at VDDFigure 6-18 Response after coming out of Power-On reset at VDD
DRV81004-Q1 Response after a command syntax errorFigure 6-19 Response after a command syntax error

A summary of all possible SPI commands is presented below, including the answer that DRV81004-Q1 sends back at the next transmission.

Table 6-6 SPI Command summary

Requested Operation

Frame sent to SDI pin

Frame received from SDO pin with the next command

Read Standard Diagnosis0xxxxxxxxxxxxx01b (xxxxxxxxxxxxb = don

't care)

0dddddddddddddddb (Standard Diagnosis)
Write 8 bit register10ppppqqrrrrrrrrb where: ppppb = register address ADDR0, qqb = register address ADDR1, rrrrrrrrb = new register content0dddddddddddddddb (Standard Diagnosis)
Read 8 bit registers01ppppqqxxxxxx10b where: ppppb = register address ADDR0, qqb = register address ADDR1, xxxxxxb = don't care10ppppqqrrrrrrrrb where: ppppb = register address ADDR0c, qqb = register address ADDR1, rrrrrrrrb = register content
“p” = address bits for ADDR0 field, “q” = address bit for ADDR1 field, “r” = register content, “d” = diagnostic bit