SLOSE97A
November 2024 – December 2024
DRV81008-Q1
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.5.1
SPI Timing Requirements
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Control Pins
6.3.1.1
Input Pins
6.3.1.2
nSLEEP Pin
6.3.2
Power Supply
6.3.2.1
Modes of Operation
6.3.2.1.1
Power-up
6.3.2.1.2
Sleep mode
6.3.2.1.3
Idle mode
6.3.2.1.4
Active mode
6.3.2.1.5
Limp Home mode
6.3.2.2
Reset condition
6.3.3
Power Stage
6.3.3.1
Switching Resistive Loads
6.3.3.2
Inductive Output Clamp
6.3.3.3
Maximum Load Inductance
6.3.3.4
Switching Channels in parallel
6.3.4
Protection and Diagnostics
6.3.4.1
Undervoltage on VM
6.3.4.2
Overcurrent Protection
6.3.4.3
Over Temperature Protection
6.3.4.4
Over Temperature Warning
6.3.4.5
Over Temperature and Overcurrent Protection in Limp Home mode
6.3.4.6
Reverse Polarity Protection
6.3.4.7
Over Voltage Protection
6.3.4.8
Output Status Monitor
6.3.5
SPI Communication
6.3.5.1
SPI Signal Description
6.3.5.1.1
Chip Select (nSCS)
6.3.5.1.1.1
Logic high to logic low Transition
6.3.5.1.1.2
Logic low to logic high Transition
6.3.5.1.2
Serial Clock (SCLK)
6.3.5.1.3
Serial Input (SDI)
6.3.5.1.4
Serial Output (SDO)
6.3.5.2
Daisy Chain Capability
6.3.5.3
SPI Protocol
6.3.5.4
SPI Registers
6.3.5.4.1
Standard Diagnosis Register
6.3.5.4.2
Output control register
6.3.5.4.3
Input 0 Mapping Register
6.3.5.4.4
Input 1 Mapping Register
6.3.5.4.5
Input Status Monitor Register
6.3.5.4.6
Open Load Current Control Register
6.3.5.4.7
Output Status Monitor Register
6.3.5.4.8
Configuration Register
6.3.5.4.9
Output Clear Latch Register
6.3.5.4.10
Configuration Register 2
7
Application and Implementation
7.1
Application Information
7.1.1
Typical Application
7.1.2
Suggested External Components
7.1.3
Application Plots
7.2
Layout
7.2.1
Layout Guidelines
7.2.2
Package Footprint Compatibility
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Support Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PWP|24
MPDS372A
Thermal pad, mechanical data (Package|Pins)
PWP|24
PPTD401
Orderable Information
slose97a_oa
1
Features
3 V to 40 V
Analog supply voltage
Cranking capability down to 3 V
Supports LV124 Automotive standard
3 V to 5.5 V
Digital supply voltage
Compatible with 3.3 V and 5 V microcontrollers
42 V
minimum drain to source clamping voltage
R
DS(ON)
:
700 mΩ
typical at 12 V, 25 °C
Current:
330 mA
per output at 85 °C, with all channels ON
2 parallel inputs
with mapping functionality
Fail-safe activation in
Limp Home
mode
Using nSLEEP and IN pins
Low-current sleep mode
< 3 μA for T
J
≤ 85 °C using nSLEEP pin
16-bit SPI interface for control and diagnosis
Daisy Chain capability
Compatible with 8-bit SPI devices
Supports various
protection features
-
Integrated Reverse battery protection
Short circuit to ground and battery protection
Stable behavior at under voltage conditions
Over Current latch OFF
Overtemperature warning
Thermal shutdown latch OFF
Overvoltage protection
Loss of battery and loss of ground protection
Electrostatic discharge (ESD) protection
Supports several
diagnostic features
-
Diagnostic information via SPI register
Over Load detection in ON state
Open Load detection in OFF state
Input and Output Status Monitor