SLLSFA9B July   2020  – June 2021 DRV8106-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8106-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Wide Common Mode Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8.6 VCP Charge Pump Undervoltage Lockout (VCP_UV)

If at any time the voltage on the VCP pin falls below the VVCP_UV threshold for longer than the tVCP_UV_DG time, the DRV8106-Q1 detects a VCP undervoltage condition. After detecting the undervoltage condition, the gate driver pull downs are enabled and nFAULT pin, FAULT register bit, and VCP_UV register bit asserted. The undervoltage threshold can be adjusted through the VCP_UV_LVL register setting.

On SPI device variants, the VCP undervoltage monitor can recover in two different modes set through the VCP_UV_MODE register setting.

  • Latched Fault Mode: Additionally the charge pump is disabled in latched fault mode. After the undervoltage condition is removed, the fault state remains latched and charge pump disabled until CLR_FLT is issued.
  • Automatic Recovery Mode: After the undervoltage condition is removed, the nFAULT pin and FAULT register bit are automatically cleared and the driver automatically reenabled. The VCP_UV register bit remains latched until CLR_FLT is issued.

On H/W device variants, the VCP undervoltage monitor is fixed to automatic recovery mode and the threshold to 2-V.