SLLSFA9B July   2020  – June 2021 DRV8106-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Descriptions
  4. Revision History
  5. Pin Configuration
    1.     DRV8106-Q1_RHB Package (VQFN) Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Wide Common Mode Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SPI Interface for Multiple Slaves in Daisy Chain

The DRV8106-Q1 device can be connected in a daisy chain configuration to save GPIO ports when multiple devices are communicating to the same MCU. Figure 7-21 shows the topology when 3 devices are connected in series with waveforms.

GUID-DB7D7F43-8B97-4907-911F-420C2DB3A3E9-low.gifFigure 7-21 Daisy Chain SPI Operation

The first device in the chain shown above receives data from the master controller in the following format. See SDI1 in Figure 7-21

  • 2 bytes of Header
  • 3 bytes of Address
  • 3 bytes of Data

After the data has been transmitted through the chain, the master controller receives it in the following format. See SDO3 in Figure 7-21

  • 3 bytes of Status
  • 2 bytes of Header (should be identical to the information controller sent)
  • 3 bytes of Report

The Header bytes contain information of the number of devices connected in the chain, and a global clear fault command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal. N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 7-22. Up to 63 devices can be connected in series per daisy chain connection.

The 5 LSBs of the HDR2 register are don’t care bits that can be used by the MCU to determine integrity of the daisy chain connection. Header bytes must start with 1 and 0 for the two MSBs.

GUID-05560C41-139F-4D36-9B8E-0B2C004FCF22-low.gifFigure 7-22 Header Bits

The Status byte provides information about the fault status register for each device in the daisy chain as shown in Figure 7-23. That way the master controller does not have to initiate a read command to read the fault status from any particular device. This saves the controller additional read commands and makes the system more efficient to determine fault conditions flagged in a device.

GUID-54D37D09-A72B-4D54-A527-F4834212311D-low.gifFigure 7-23 Daisy Chain Read Registers

When data passes through a device, it determines the position of itself in the chain by counting the number of Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in the chain will receive two Status bytes before receiving HDR1 byte, followed by HDR2 byte.

From the two Status bytes it knows that its position is second in the chain, and from HDR2 byte it knows how many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster communication without adding latency to the system for up to 63 devices in the chain.

The address and data bytes remain the same with respect to a single device connection. The Report bytes (R1 through R3), as shown in the figure above, is the content of the register being accessed.

GUID-CC4ED4BE-9AD2-440D-8237-39FA54FBCD6E-low.gifFigure 7-24 SPI Slave Timing Diagram