SLVSG63A January   2023  – March 2024 DRV8143-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 HW Variant
      1. 5.1.1 VQFN-HR (14) package
      2. 5.1.2 HVSSOP (28) package
    2. 5.2 SPI Variant
      1. 5.2.1 HVSSOP (28) package
      2. 5.2.2 VQFN-HR (14) package
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1  Power Supply & Initialization
      2. 6.5.2  Logic I/Os
      3. 6.5.3  SPI I/Os
      4. 6.5.4  Configuration Pins - HW Variant Only
      5. 6.5.5  Power FET Parameters
      6. 6.5.6  Switching Parameters with High-Side Recirculation
      7. 6.5.7  Switching Parameters with Low-Side Recirculation
      8. 6.5.8  IPROPI & ITRIP Regulation
      9. 6.5.9  Over Current Protection (OCP)
      10. 6.5.10 Over Temperature Protection (TSD)
      11. 6.5.11 Voltage Monitoring
      12. 6.5.12 Load Monitoring
      13. 6.5.13 Fault Retry Setting
      14. 6.5.14 Transient Thermal Impedance & Current Capability
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Waveforms
      1. 6.7.1 Output switching transients
        1. 6.7.1.1 High-Side Recirculation
        2. 6.7.1.2 Low-Side Recirculation
      2. 6.7.2 Wake-up Transients
        1. 6.7.2.1 HW Variant
        2. 6.7.2.2 SPI Variant
      3. 6.7.3 Fault Reaction Transients
        1. 6.7.3.1 Retry setting
        2. 6.7.3.2 Latch setting
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 HW Variant
      2. 7.2.2 SPI Variant
    3. 7.3 Feature Description
      1. 7.3.1 External Components
        1. 7.3.1.1 HW Variant
        2. 7.3.1.2 SPI Variant
      2. 7.3.2 Bridge Control
        1. 7.3.2.1 Register - Pin Control - SPI Variant Only
      3. 7.3.3 Device Configuration
        1. 7.3.3.1 Slew Rate (SR)
        2. 7.3.3.2 IPROPI
        3. 7.3.3.3 ITRIP Regulation
        4. 7.3.3.4 DIAG
          1. 7.3.3.4.1 HW variant
          2. 7.3.3.4.2 SPI variant
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Over Current Protection (OCP)
        2. 7.3.4.2 Over Temperature Protection (TSD)
        3. 7.3.4.3 Off-State Diagnostics (OLP)
        4. 7.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only
        5. 7.3.4.5 VM Over Voltage Monitor
        6. 7.3.4.6 VM Under Voltage Monitor
        7. 7.3.4.7 Charge pump under voltage monitor
        8. 7.3.4.8 Power On Reset (POR)
        9. 7.3.4.9 Event Priority
    4. 7.4 Programming - SPI Variant Only
      1. 7.4.1 SPI Interface
      2. 7.4.2 Standard Frame
      3. 7.4.3 SPI Interface for Multiple Peripherals
        1. 7.4.3.1 Daisy Chain Frame for Multiple Peripherals
  9. 8 Register Map - SPI Variant Only
    1. 8.1 User Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Load Summary
    2. 9.2 Typical Application
      1. 9.2.1 HW Variant
      2. 9.2.2 SPI Variant
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Bulk Capacitance Sizing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 summarizes the RON and package differences between devices in the DRV814x-Q1 family.

Table 4-1 Device Comparison
PART NUMBER(1)(LS + HS) RONIOUT MAXPACKAGEBODY SIZE (nominal)Variants
DRV8143-Q142mΩ20AVQFN-HR (14)3mm X 4.5mmHW (H), SPI (S)
DRV8143-Q149mΩ20AHVSSOP (28)3mm X 7.3mmHW (H), SPI (P)
DRV8144-Q123.6mΩ30AVQFN-HR (16)3mm X 6mmHW (H), SPI (S)
DRV8145-Q116mΩ46AVQFN-HR (16)3.5mm X 5.5mmHW (H), SPI (S)
DRV8145-Q119mΩ46AHTSSOP (28)4.4mm X 9.7mmSPI (P)
(1) This is the product datasheet for the DRV8143-Q1. Please reference other device variant data sheets for additional information.

Table 4-2 summarizes the feature differences between the SPI and HW interface variants in the DRV814x-Q1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback, redundant driver shutoff, improved Pin FMEA, and additional features.

In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant. The SPI (P) variant supports an external, low voltage 5V supply to the device through the VDD pin for the device logic, whereas in the SPI (S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant avoids device brown out (reset of device) during VM under voltage transients.

Note: DRV8144-Q1 is NOT available in SPI(P) variant.
Table 4-2 SPI Variant vs HW Variant Comparison
FUNCTIONHW (H) VariantSPI (S) VariantSPI (P) Variant
Bridge controlPin onlyIndividual pin "and/or" register bit with pin status indication (Refer Register Pin control)
Sleep functionAvailable through nSLEEP pinNot available
External logic supply to the deviceNot supportedNot supportedSupported through VDD pin
Clear fault commandReset pulse on nSLEEP pinSPI CLR_FAULT command
Slew rate6 levels8 levels
Over current protection (OCP)Fixed at the highest setting3 choices for thresholds, 4 choices for filter time
ITRIP regulation5 levels with disable & fixed TOFF time7 levels with disable & indication, with programmable TOFF time
Individual fault reaction configuration between retry or latched behaviorNot supported, either all latched or all retrySupported
Detailed fault logging and device status feedbackNot supported, nFAULT pin monitoring necessarySupported, nFAULT pin monitoring optional
VM over voltageFixed4 threshold choices
On-state (Active) diagnosticsNot supportedSupported for high-side loads
Spread spectrum clocking (SSC)Not supportedSupported
Table 4-3 Differentiating between devices in the family
DevicePackage SymbolizationDEVICE_ID Register
DRV8143H-Q18143HNot applicable
DRV8144H-Q18144HNot applicable
DRV8145H-Q18145HNot applicable
DRV8143S-Q18143S0 x BA
DRV8144S-Q18144S0 x CA
DRV8145S-Q18145S0 x DA
DRV8143P-Q18143P0 x BE
DRV8145P-Q18145P0 x DE