SLVSG63A January 2023 – March 2024 DRV8143-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIL_nSLEEP | Input logic low voltage | nSLEEP pin | 0.65 | V | ||
VIH_nSLEEP | Input logic high voltage | nSLEEP pin | 1.55 | V | ||
VIHYS_nSLEEP | Input hysteresis | nSLEEP pin | 200 | mV | ||
VIL | Input logic low voltage | DRVOFF, IN pins | 0.7 | V | ||
VIH | Input logic high voltage | DRVOFF, IN pins | 1.5 | V | ||
VIHYS | Input hysteresis | DRVOFF, IN pins | 100 | mV | ||
RPD_nSLEEP | Internal pull-down resistance on nSLEEP to GND | Measured at min VIL level | 100 | 400 | KΩ | |
RPU | Internal pull-up resistance to VDD (reverse current blocked) on DRVOFF | Measured at min VIH level | 200 | 550 | KΩ | |
RPD | Internal pull-down resistance to GND on IN | Measured at max VIL level | 200 | 500 | KΩ | |
InFAULT_PD | Sink current to GND on nFAULT pin when asserted low | VnFAULT = 0.3 V | 5 | mA |