SLVSG63A January 2023 – March 2024 DRV8143-Q1
PRODUCTION DATA
The following figure shows a layout example for a 4cm X 4cm x 1.6mm, 4 layer PCB for a leaded package device. The 4 layers uses 2oz copper on top/ bottom signal layers and 1oz copper on internal supply layers, with 0.3mm thermal via drill diameter, 0.025mm Cu plating, 1mm minimum via pitch. The same layout can be adopted for the non-leaded VQFN-HR package as well. The Section 6.5.14 for the 4cm X 4cm X 1.6mm is based on a similar layout.
Note: The layout example shown is for a full-bridge topology using DRV814xQ1 device in VQFN-HR package.