SLVSGV9 august 2023 DRV8213
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES, DSG (VM) | ||||||
IVMQ | VM sleep mode current | IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, TJ = 27°C | 20 | 60 | nA | |
IVM | VM active mode current | IN1 = 3.3 V, IN2 = 0 V | 1.2 | 1.9 | mA | |
tWAKE | Turnon time | Sleep mode to active mode delay | 250 | μs | ||
tAUTOSLEEP | Autosleep turnoff time | Active mode to autosleep mode delay | 0.7 | 1 | 1.3 | ms |
fVCP | Charge pump switching frequency | 6000 | kHz | |||
POWER SUPPLIES, RTE (VM, VCC) | ||||||
IVMQ | VM sleep mode current | IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C | 10 | 20 | nA | |
IVM | VM active mode current | IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V | 0.83 | 1 | mA | |
IVCCQ | VCC sleep mode current | IN1 = IN2 = 0 V, after waiting tAUTOSLEEP, VVM = 5 V, VVCC = 3.3 V, TJ = 27°C | 6 | 12 | nA | |
IVCC | VCC active mode current | IN1 = 3.3 V, IN2 = 0 V, VVM = 5 V, VVCC = 3.3 V | 0.46 | 0.6 | mA | |
tWAKE | Turnon time | Sleep mode to active mode delay | 250 | μs | ||
tAUTOSLEEP | Autosleep turnoff time | Active mode to autosleep mode delay | 0.75 | 0.9 | 1.05 | ms |
LOGIC-LEVEL INPUTS (IN1, IN2) | ||||||
VIL | Input logic low voltage | 0 | 0.4 | V | ||
VIH | Input logic high voltage | 1.45 | 5.5 | V | ||
VHYS | Input hysteresis | 40 | mV | |||
IIL | Input logic low current | VI = 0 V | -1 | 1 | µA | |
IIH | Input logic high current | VINx = 5 V | 15 | 35 | µA | |
VnSTALL = VCC | 40 | nA | ||||
RPD | Input pulldown resistance, INx | 200 | kΩ | |||
tDEGLITCH | Input logic deglitch, INx | 50 | ns | |||
TRI-LEVEL INPUTS (IMODE, SMODE) | ||||||
VTHYS | Tri-level input logic low voltage | 0 | 0.4 | V | ||
ITIL | Tri-level input Hi-Z voltage | 0.75 | 1.05 | V | ||
ITIZ | Tri-level input logic high voltage | 1.45 | 5.5 | V | ||
RTPD | Tri-level pulldown resistance | to GND | 83 | kΩ | ||
ITPU | Tri-level pullup current | to VCC | 10.5 | µA | ||
OPEN-DRAIN OUTPUTS (nFAULT, nSTALL) | ||||||
VOL | Output logic low voltage | IOD = 5 mA | 0.4 | V | ||
IOZ | Output logic high current | VOD = VCC | -1 | 1 | µA | |
DRIVER OUTPUTS (OUTx) | ||||||
RDS(ON)_HS | High-side MOSFET on resistance | IOUTx = 1 A | 120 | 280 | mΩ | |
RDS(ON)_LS | Low-side MOSFET on resistance, 350mA to 2A | GAINSEL = Low | 120 | 260 | mΩ | |
RDS(ON)_LS | Low-side MOSFET on resistance, 60mA to 350mA | GAINSEL = High-Z | 460 | 900 | mΩ | |
RDS(ON)_LS | Low-side MOSFET on resistance, 10mA to 60mA | GAINSEL = High | 2100 | 4000 | mΩ | |
VSD | Body diode forward voltage | IOUTx = -1 A | 0.9 | V | ||
tRISE | Output rise time | VOUTx rising from 10% to 90% of VVM | 70 | ns | ||
tFALL | Output fall time | VOUTx falling from 90% to 10% of VVM | 40 | ns | ||
tPDR | Input high to output high propagation delay | Input to OUTx | 450 | ns | ||
tPDF | Input low to output low propagation delay | Input to OUTx | 450 | ns | ||
tDEAD | Output dead time | 500 | ns | |||
CURRENT SENSE AND REGULATION (IPROPI, VREF) | ||||||
VREF_INT | Internal reference voltage | SMODE = Open for RTE package and for DSG package | 470 | 510 | 550 | mV |
AIPROPI_H | Current scaling factor | GAINSEL = Low | 205 | µA/A | ||
AIPROPI_M | Current scaling factor | GAINSEL = High-Z | 1050 | µA/A | ||
AIPROPI_L | Current scaling factor | GAINSEL = High | 4900 | µA/A | ||
AERR_H | Current mirror total error, 350 mA to 2 A | GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V | -6 | 6 | % | |
AERR_H | Current mirror total error, 350 mA to 2 A | GAINSEL = Low, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V | -6 | 6 | % | |
AERR_M | Current mirror total error, 60 mA to 350 mA | GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V | -6 | 6 | % | |
GAINSEL = High-Z, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V | -6 | 6 | % | |||
AERR_L | Current mirror total error, 10 mA to 60 mA | GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V | -6 | 6 | % | |
GAINSEL = High, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V | -6 | 6 | % | |||
tOFF | Current regulation off time | 20 | µs | |||
tBLANK | Current regulation blanking time | 1.8 | µs | |||
tDELAY | Current sense delay time | 1.5 | µs | |||
tDEG | Current regulation and stall detection deglitch time | 2 | µs | |||
HARDWARE STALL DETECTION (TINRUSH) | ||||||
VTINRUSH_trip | Threshold voltage for setting tINRUSH timing | 0.97 | 1 | 1.03 | V | |
ITINRUSH | Current sourced out of the TINRUSH pin | Inputs transition to a state other than IN1=IN2=0, VTINRUSH < VTINRUSH_trip | 8 | 10 | 12 | µA |
tdischarge | TINRUSH capacitor discharge time | 0.8 nF ≤ CTINRUSH ≤ 0.8 µF | 100 | µs | ||
tSTALL_RETRY | IN1/IN2 = 0/0 duration to recover from Stall (retry type) | 350 | 900 | µs | ||
PROTECTION CIRCUITS | ||||||
VUVLO_VM | VM supply undervoltage lockout (UVLO), DSG | Supply rising | 1.65 | V | ||
Supply falling | 1.30 | V | ||||
VUVLO_VCC | VCC supply undervoltage lockout (UVLO), RTE | Supply rising | 1.65 | V | ||
Supply falling | 1.30 | V | ||||
VUVLO_HYS | Supply UVLO hysteresis | Rising to falling threshold | 150 | mV | ||
tUVLO | Supply undervoltage deglitch time | VVM falling (DSG) or VVCC falling (RTE) to OUTx disabled | 10 | µs | ||
IOCP | Overcurrent protection trip point, 350mA to 2A | 4 | A | |||
IOCP | Overcurrent protection trip point, 60mA to 350mA | 0.8 | A | |||
IOCP | Overcurrent protection trip point, 10mA to 60mA | 0.16 | A | |||
tOCP | Overcurrent protection deglitch time | 4.2 | µs | |||
tRETRY | Fault retry time | 1.5 | ms | |||
TTSD | Thermal shutdown temperature | 165 | 175 | 185 | °C | |
THYS | Thermal shutdown hysteresis | 17 | °C |