SLVSH04 November 2023 DRV8214
PRODUCTION DATA
Whenever the VCC supply voltage falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETs are disabled, all internal logic is reset and nFAULT is pulled low.
The device allows the VM supply to dip all the way to 0 V. Normal operation resumes when the VCC voltage rises above the VUVLO rising threshold as shown in (FIGURE BELOW). (TABLE BELOW) summarizes the conditions when the device enters UVLO.
The NPOR bit is reset and latched low once VCC goes above the UVLO threshold.
NPOR remains in reset condition until cleared through the CLR_FLT bit.
After power up, NPOR is automatically latched high once the CLR_FLT command is issued.
VVM | VVCC | Device Response | IPROPI |
---|---|---|---|
0 V to VVM_MAX | <1.65 V | UVLO | Not available |
0 V to VVM_MAX | >1.65 V | Normal Operation | Available for VVM > 1.65 V |