SLVSH04 November 2023 DRV8214
PRODUCTION DATA
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this analog current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable, FAULT and OCP bits become 1b and nFAULT is pulled low.
The OCP_MODE bit programs the response of the device to overcurrent event. The device can either latch-off or perform automatic retry to recover from an overcurrent event.
In automatic retry mode, the MOSFETs will be disabled and the nFAULT pin driven low for a duration of tRETRY. After tRETRY, the MOSFETs are re-enabled according to the control inputs. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes. This is explained by the following diagram -
In latch-off mode, the MOSFETs will remain disabled and the nFAULT pin will be driven low until the device is reset by a CLR_FLT command or by cycling the VM power supply.
Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and IPROPI settings.