SLVSFU5B February   2020  – August 2021 DRV8220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 External Components
      2. 8.3.2 Control Modes
        1. 8.3.2.1 PWM Control Mode (DSG: MODE = 0 and DRL)
        2. 8.3.2.2 PH/EN Control Mode (DSG: MODE = 1)
        3. 8.3.2.3 Half-Bridge Control Mode (DSG: MODE = Hi-Z)
      3. 8.3.3 Protection Circuits
        1. 8.3.3.1 Supply Undervoltage Lockout (UVLO)
        2. 8.3.3.2 OUTx Overcurrent Protection (OCP)
        3. 8.3.3.3 Thermal Shutdown (TSD)
      4. 8.3.4 Pin Diagrams
        1. 8.3.4.1 Logic-Level Inputs
        2. 8.3.4.2 Tri-Level Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
      2. 8.4.2 Low-Power Sleep Mode
      3. 8.4.3 Fault Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Full-Bridge Driving
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Supply Voltage
          2. 9.2.1.2.2 Control Interface
          3. 9.2.1.2.3 Low-Power Operation
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Half-Bridge Driving
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Supply Voltage
          2. 9.2.2.2.2 Control Interface
          3. 9.2.2.2.3 Low-Power Operation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Dual-Coil Relay Driving
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Supply Voltage
          2. 9.2.3.2.2 Control Interface
          3. 9.2.3.2.3 Low-Power Operation
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Current Sense
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Shunt Resistor Sizing
          2. 9.2.4.2.2 RC Filter
    3. 9.3 Current Capability and Thermal Performance
      1. 9.3.1 Power Dissipation and Output Current Capability
      2. 9.3.2 Thermal Performance
        1. 9.3.2.1 Steady-State Thermal Performance
        2. 9.3.2.2 Transient Thermal Performance
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Low-Power Sleep Mode

The DRV8220 supports a low-power sleep mode to reduce current consumption from VM when the driver is not active. In low-power sleep mode, the device draws minimal current denoted by IVMQ. There are two ways to enter low-power sleep mode in the DSG package: autosleep and using the nSLEEP pin. Table 8-8 describes how to enter low-power sleep mode. The DRL package variant only supports autosleep mode.

Table 8-8 DRV8220 sleep mode summary
Variant Input pin state OUT1 OUT2 Description
DRL IN1 = IN2 = 0 Hi-Z Hi-Z Autosleep for PWM interface: Upon entering this state, the outputs are disabled. The device remains in Active Mode for tSLEEP, then goes into low-power mode.
DSG MODE = 0, IN1 = IN2 = 0 Hi-Z Hi-Z
MODE = 1, EN = 0 L → Hi-Z L → Hi-Z Autosleep for PH/EN interface: Upon entering this state, both outputs go into brake mode by turning the low-side FETs on. The device remains in this state for tSLEEP, then goes into low-power mode. Once in low-power mode, the outputs are disabled.
nSLEEP = 0 Hi-Z Hi-Z Sleep pin: When the nSLEEP pin goes low, the outputs are disabled, and the device goes into low-power sleep mode immediately.

The device returns to active mode when the input pins move to a state other than the ones in Table 8-8. To wake up the device from autosleep mode, the INx pins or EN pin (depending on MODE state and package variant) must be asserted high for longer than tWAKE before receiving PWM input signals. When using the nSLEEP pin, nSLEEP must be asserted high longer than tWAKE and the INx or EN pins must not be in an autosleep state.

In the DSG package, TI recommends tying the nSLEEP pin to the logic supply rail when using autosleep in PWM or PH/EN interface modes. For applications where a microcontroller controls nSLEEP, designers must ensure that nSLEEP is not floating while VM > VUVLO. This may cause unintended outputs, depending on the state of the MODE, IN1/PH, and IN2/EN pins. If this condition may occur in the system, then TI recommends using a 100 kΩ pulldown resistor on nSLEEP.