SLVSH03 December 2023 DRV8234
PRODUCTION DATA
All the outputs are disabled (High-Z)
The internal charge pump is disabled
nFAULT is driven low
Normal operation resumes when the VM voltage recovers above the UVLO rising threshold.
If the voltage on the VM pin falls below the UVLO falling threshold voltage, but is above the VRST:
I2C communication is available and the digital core of the device is active
The FAULT and UVLO bits are made high
The nFAULT pin is driven low
From this condition, if the VM voltage recovers above the UVLO rising threshold voltage:
nFAULT pin is released (is pulled-up to the external voltage)
The FAULT bit is reset
The UVLO bit remains latched high until cleared through the CLR_FLT command.
I2C communication is unavailable and the digital core is shutdown
The FAULT and UVLO bits are low
The nFAULT pin is high
The digital core comes alive
UVLO bit stays low
The FAULT bit is made high
The nFAULT pin is pulled low
When the VM voltage exceeds the VM UVLO rising threshold
FAULT bit is reset
UVLO bit stays low
nFAULT pin is pulled high.